[PATCH 1/6] dt-bindings: PCI: rcar-gen4-pci-host: Document Application/Local register reset

[PATCH 1/6] dt-bindings: PCI: rcar-gen4-pci-host: Document Application/Local register reset

[Marek Vasut]

The R-Car Gen4 PCIe controller does contain core reset, which puts
the controller back into well defined state, but it does also tear
down the PCIe link. This is called Application/Local register reset
in the documentation. Document this reset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 .../devicetree/bindings/pci/rcar-gen4-pci-host.yaml    | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
index 64f456c6a75a1..8a06a25e266b5 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -57,11 +57,15 @@ properties:
     maxItems: 1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   reset-names:
+    minItems: 1
+    maxItems: 2
     items:
       - const: pwr
+      - const: core
 
   max-link-speed:
     maximum: 4
@@ -111,8 +115,8 @@ examples:
             clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
             clock-names = "core", "ref";
             power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-            resets = <&cpg 624>;
-            reset-names = "pwr";
+            resets = <&cpg 624>,<&cpg 1121>;
+            reset-names = "pwr", "core";
             max-link-speed = <4>;
             num-lanes = <2>;
             #address-cells = <3>;
-- 
2.53.0

[PATCH 2/6] dt-bindings: PCI: rcar-gen4-pci-ep: Document Application/Local register reset

[Marek Vasut]

The R-Car Gen4 PCIe controller does contain core reset, which puts
the controller back into well defined state, but it does also tear
down the PCIe link. This is called Application/Local register reset
in the documentation. Document this reset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 .../devicetree/bindings/pci/rcar-gen4-pci-ep.yaml      | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
index b23293314a6d0..a983aa015cd1b 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
@@ -56,11 +56,15 @@ properties:
     maxItems: 1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   reset-names:
+    minItems: 1
+    maxItems: 2
     items:
       - const: pwr
+      - const: core
 
   max-link-speed:
     maximum: 4
@@ -109,8 +113,8 @@ examples:
             clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
             clock-names = "core", "ref";
             power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-            resets = <&cpg 624>;
-            reset-names = "pwr";
+            resets = <&cpg 624>,<&cpg 1121>;
+            reset-names = "pwr", "core";
             max-link-speed = <4>;
             num-lanes = <2>;
             max-functions = /bits/ 8 <2>;
-- 
2.53.0

[PATCH 3/6] PCI: rcar-gen4: Add Application/Local register reset control

[Marek Vasut]

The R-Car Gen4 PCIe controller does contain core reset, which puts
the controller back into well defined state, but it does also tear
down the PCIe link. This is called Application/Local register reset
in the documentation.

Deassert the core reset after the core clock have been enabled, and
assert the core reset in case of error or when shutting down the
controller.

This also fixes reinitialization failure of the controller, where if
the controller driver is unbind and bind again via sysfs attributes,
the controller driver will fail to probe the second time because it
fails to access the controller DBI, which returns all zeroes unless
the core reset is toggled. The following commands trigger this fault
on R-Car V4H:

$ echo e65d0000.pcie > /sys/bus/platform/drivers/pcie-rcar-gen4/unbind
$ echo e65d0000.pcie > /sys/bus/platform/drivers/pcie-rcar-gen4/bind

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 drivers/pci/controller/dwc/pcie-rcar-gen4.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index f938430644860..ceffaa2e4cf99 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -197,6 +197,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
 		return ret;
 	}
 
+	reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
+
 	if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
 		reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
 		/*
@@ -247,6 +249,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
 	return 0;
 
 err_unprepare:
+	reset_control_assert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
 	clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
 
 	return ret;
@@ -257,6 +260,7 @@ static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
 	struct dw_pcie *dw = &rcar->dw;
 
 	reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+	reset_control_assert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
 	clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
 }
 
-- 
2.53.0

[PATCH 4/6] arm64: dts: renesas: r8a779f0: Add PCIe Application/Local register reset

[Marek Vasut]

Renesas R-Car S4 documentation R19UH0161EJ0140 Rev.1.40 , Jul. 31, 2026
chapter 9A.1.1.12 Software Reset Control Register 11 (SRCR11) bits 22
and 21 describe PCIEC ch1/ch0 Application/Local register reset. Add the
matching reset into both RC and EP DT nodes of both PCIe controllers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 69c247b7f0e28..878b1d53fa371 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -790,8 +790,8 @@ pciec0: pcie@e65d0000 {
 			clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-			resets = <&cpg 624>;
-			reset-names = "pwr";
+			resets = <&cpg 624>, <&cpg 1121>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			#address-cells = <3>;
@@ -827,8 +827,8 @@ pciec1: pcie@e65d8000 {
 			clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-			resets = <&cpg 625>;
-			reset-names = "pwr";
+			resets = <&cpg 625>, <&cpg 1122>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			#address-cells = <3>;
@@ -863,8 +863,8 @@ pciec0_ep: pcie-ep@e65d0000 {
 			clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-			resets = <&cpg 624>;
-			reset-names = "pwr";
+			resets = <&cpg 624>, <&cpg 1121>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			max-functions = /bits/ 8 <2>;
@@ -886,8 +886,8 @@ pciec1_ep: pcie-ep@e65d8000 {
 			clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-			resets = <&cpg 625>;
-			reset-names = "pwr";
+			resets = <&cpg 625>, <&cpg 1122>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			max-functions = /bits/ 8 <2>;
-- 
2.53.0

[PATCH 5/6] arm64: dts: renesas: r8a779g0: Add PCIe Application/Local register reset

[Marek Vasut]

Renesas R-Car V4H documentation R19UH0186EJ0140 Rev.1.40 , Aug. 7, 2026
attachment R-CarV4H_UM_009_SRCRn_FSRCHKRAn_FSRCHKRBn_r1p40.xlsx rows 410
and 411 describe PCIEC ch1/ch0 Application/Local register reset. Add the
matching reset into both RC and EP DT nodes of both PCIe controllers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index ea6495261c2bb..fbcd9d37eb8a2 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -806,8 +806,8 @@ pciec0: pcie@e65d0000 {
 			clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
-			resets = <&cpg 624>;
-			reset-names = "pwr";
+			resets = <&cpg 624>, <&cpg 1121>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			msi-parent = <&its>;
 			num-lanes = <2>;
@@ -854,8 +854,8 @@ pciec1: pcie@e65d8000 {
 			clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
-			resets = <&cpg 625>;
-			reset-names = "pwr";
+			resets = <&cpg 625>, <&cpg 1122>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			msi-parent = <&its>;
 			num-lanes = <2>;
@@ -901,8 +901,8 @@ pciec0_ep: pcie-ep@e65d0000 {
 			clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
-			resets = <&cpg 624>;
-			reset-names = "pwr";
+			resets = <&cpg 624>, <&cpg 1121>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			max-functions = /bits/ 8 <2>;
@@ -924,8 +924,8 @@ pciec1_ep: pcie-ep@e65d8000 {
 			clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
-			resets = <&cpg 625>;
-			reset-names = "pwr";
+			resets = <&cpg 625>, <&cpg 1122>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			max-functions = /bits/ 8 <2>;
-- 
2.53.0

[PATCH 6/6] arm64: dts: renesas: r8a779h0: Add PCIe Application/Local register reset

[Marek Vasut]

Renesas R-Car V4M documentation R19UH0217EJ0110 Rev.1.10 , Jun. 30, 2026
attachment R-CarV4M_UM_009_SRCRn_FSRCHKRAn_FSRCHKRBn_r1p10.xlsx row 411
describes PCIEC ch0 Application/Local register reset. Add the reset into
both RC and EP DT nodes of PCIe controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Koichiro Den <den@valinux.co.jp>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index aca6ffc68c30a..c66fb22d72aa8 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -688,8 +688,8 @@ pciec0: pcie@e65d0000 {
 			clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779H0_PD_A2PCIPHY>;
-			resets = <&cpg 624>;
-			reset-names = "pwr";
+			resets = <&cpg 624>, <&cpg 1121>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			#address-cells = <3>;
@@ -724,8 +724,8 @@ pciec0_ep: pcie-ep@e65d0000 {
 			clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 			clock-names = "core", "ref";
 			power-domains = <&sysc R8A779H0_PD_A2PCIPHY>;
-			resets = <&cpg 624>;
-			reset-names = "pwr";
+			resets = <&cpg 624>, <&cpg 1121>;
+			reset-names = "pwr", "core";
 			max-link-speed = <4>;
 			num-lanes = <2>;
 			max-functions = /bits/ 8 <2>;
-- 
2.53.0

Re: [PATCH 2/6] dt-bindings: PCI: rcar-gen4-pci-ep: Document Application/Local register reset

[sashiko-bot]

> The R-Car Gen4 PCIe controller does contain core reset, which puts
> the controller back into well defined state, but it does also tear
> down the PCIe link. This is called Application/Local register reset
> in the documentation. Document this reset.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903205153.283553-1-marek.vasut+renesas@mailbox.org?part=2

Re: [PATCH 1/6] dt-bindings: PCI: rcar-gen4-pci-host: Document Application/Local register reset

[sashiko-bot]

> The R-Car Gen4 PCIe controller does contain core reset, which puts
> the controller back into well defined state, but it does also tear
> down the PCIe link. This is called Application/Local register reset
> in the documentation. Document this reset.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903205153.283553-1-marek.vasut+renesas@mailbox.org?part=1

Re: [PATCH 4/6] arm64: dts: renesas: r8a779f0: Add PCIe Application/Local register reset

[sashiko-bot]

> Renesas R-Car S4 documentation R19UH0161EJ0140 Rev.1.40 , Jul. 31, 2026
> chapter 9A.1.1.12 Software Reset Control Register 11 (SRCR11) bits 22
> and 21 describe PCIEC ch1/ch0 Application/Local register reset. Add the
> matching reset into both RC and EP DT nodes of both PCIe controllers.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903205153.283553-1-marek.vasut+renesas@mailbox.org?part=4

Re: [PATCH 5/6] arm64: dts: renesas: r8a779g0: Add PCIe Application/Local register reset

[sashiko-bot]

> Renesas R-Car V4H documentation R19UH0186EJ0140 Rev.1.40 , Aug. 7, 2026
> attachment R-CarV4H_UM_009_SRCRn_FSRCHKRAn_FSRCHKRBn_r1p40.xlsx rows 410
> and 411 describe PCIEC ch1/ch0 Application/Local register reset. Add the
> matching reset into both RC and EP DT nodes of both PCIe controllers.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903205153.283553-1-marek.vasut+renesas@mailbox.org?part=5

Re: [PATCH 3/6] PCI: rcar-gen4: Add Application/Local register reset control

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The return value of `reset_control_deassert()` for `DW_PCIE_CORE_RST` is ignored, which can lead to a system crash (SError) if the deassertion fails.
--

commit 3d2b0c33735de6a173b91f3402a1d145ece0119d
Author: Marek Vasut <marek.vasut+renesas@mailbox.org>

PCI: rcar-gen4: Add Application/Local register reset control

This commit adds support for the Application/Local register reset control
for the R-Car Gen4 PCIe controller. It ensures the core reset is deasserted
after the core clock is enabled, and asserted on errors or shutdown to fix
a reinitialization failure when unbinding and rebinding the driver.

> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index fbe465a29068f..0c760041aacc0 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -197,6 +197,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
>  		return ret;
>  	}
>  
> +	reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);

[Severity: High]
Should the return value of reset_control_deassert() be checked here?

If the deassertion fails (e.g., returning -ENOMEM or -EIO), the PCIe core
hardware block might remain in a reset state. The code then proceeds to
access hardware registers shortly after:

rcar_gen4_pcie_common_init() {
    ...
    val = readl(rcar->base + PCIEMSR0);
    ...
}

On ARM64 platforms like R-Car, attempting MMIO reads to a peripheral that is
held in reset typically triggers a synchronous external abort (SError),
resulting in an unrecoverable kernel panic.

Since device probing can be triggered interactively via sysfs as noted in
the commit message, an unhandled reset failure could turn a normal probing
error into a system crash.

Would it be safer to check this return value and jump to err_unprepare on
failure, similar to how DW_PCIE_PWR_RST is checked later in this function?

> +
>  	if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
>  		reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
>  		/*

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903205153.283553-1-marek.vasut+renesas@mailbox.org?part=3

Re: [PATCH 6/6] arm64: dts: renesas: r8a779h0: Add PCIe Application/Local register reset

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The PCIe CORE_RST handling introduced in this series (commit "PCI: rcar-gen4: Add Application/Local register reset control") ignores the return value of `reset_control_deassert()` and fails to explicitly assert the reset before deasserting it. This violates mandatory API error-handling and fails to guarantee the state transition (toggle) required to properly reset the hardware.
--

commit 3d2b0c33735de6a173b91f3402a1d145ece0119d
Author: Marek Vasut <marek.vasut+renesas@mailbox.org>

PCI: rcar-gen4: Add Application/Local register reset control

This commit adds support for the core reset (Application/Local register
reset) in the R-Car Gen4 PCIe controller. It asserts the core reset on
shutdown or error, and deasserts it during initialization. This is
intended to fix a reinitialization failure where unbinding and rebinding
the driver fails to access the controller DBI.

> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index fbe465a29068f..0c760041aacc0 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -197,6 +197,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
>  		return ret;
>  	}
>  
> +	reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
> +

[Severity: High]
Looking at rcar_gen4_pcie_common_init() in
drivers/pci/controller/dwc/pcie-rcar-gen4.c, does this code need to check
the return value of reset_control_deassert()?

If the core reset fails to deassert, subsequent register accesses (such as
readl(rcar->base + PCIEMSR0)) can cause a synchronous external abort,
crashing the system.

Also, should this explicitly assert the reset before deasserting it to
ensure a proper state toggle?

If the bootloader or previous kernel (via kexec) leaves the controller
deasserted, the lack of an initial toggle leaves the hardware in a stale
state. This breaks the controller reinitialization fix the patch intended to
provide, since as the commit message notes, failing to toggle the reset
causes DBI accesses to fail and return zeroes.

>  	if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
>  		reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903205153.283553-1-marek.vasut+renesas@mailbox.org?part=6