* [PATCH v2 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports
2026-09-08 19:05 [PATCH v2 0/2] Fix for storage corruption w/ AMD IOMMU on 64-bit addressing Mario Limonciello
@ 2026-09-08 19:05 ` Mario Limonciello
2026-09-08 19:17 ` sashiko-bot
2026-09-08 19:06 ` [PATCH v2 2/2] Revert "ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585" Mario Limonciello
1 sibling, 1 reply; 5+ messages in thread
From: Mario Limonciello @ 2026-09-08 19:05 UTC (permalink / raw)
To: Bjorn Helgaas, Damien Le Moal, Niklas Cassel
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), H . Peter Anvin,
open list:PCI SUBSYSTEM,
open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
Mario Limonciello, david.laight.linux, John Smith,
Lennert Buytenhek, Roland Waltersson, Mikael Etienne,
Arthur Husband, Alvin Lim
There have been multiple reports of data corruption that can occur
with 64-bit DMA when the IOMMU is enabled. This occurs due to some
BIOSes enabling enhanced atomic operations on PCIe ports.
When enhanced atomic operations are enabled on PCIe ports for some
models, data corruption occurs when the 32-bit IOVA space is exhausted.
The problem is reported on storage devices, but can affect any device
that uses 64 bit DMA.
Disable enhanced atomics using SMN for NBIO 7.7 and 7.11 based models.
Cc: david.laight.linux@gmail.com
Cc: John Smith <imjohnsmith4000@gmail.com>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Niklas Cassel <cassel@kernel.org>
Cc: Roland Waltersson <roland.waltersson@netinsight.net>
Reported-by: Mikael Etienne <mikael1022bzh@gmail.com>
Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
Reported-by: Arthur Husband <artmoty@gmail.com>
Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
Reported-by: Alvin Lim <alvinwylim@gmail.com>
Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
v2:
* Apply to suspend/resume as well.
---
arch/x86/pci/fixup.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index b301c6c8df753..79e4338e4b876 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -886,6 +886,105 @@ static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
+
+/*
+ * Enhanced atomic operations can cause corruption with 64-bit IOVA
+ * on these devices.
+ */
+#define RX_ENH_ATOMIC_EN BIT(8)
+
+static const u32 nbio_7_7_pcie_smn_addrs[] = {
+ 0x111401d0,
+ 0x111411d0,
+ 0x111421d0,
+ 0x111431d0,
+ 0x111441d0,
+ 0x112401d0,
+ 0x112411d0,
+ 0x112421d0,
+ 0x112431d0,
+ 0x112441d0,
+ 0x112451d0,
+ 0x113401d0,
+ 0x114401d0,
+};
+
+static const u32 nbio_7_11_pcie_smn_addrs[] = {
+ 0x112401d0,
+ 0x112411d0,
+ 0x112421d0,
+ 0x112431d0,
+ 0x112441d0,
+ 0x112451d0,
+ 0x113401d0,
+ 0x113411d0,
+ 0x113421d0,
+ 0x113431d0,
+ 0x113441d0,
+ 0x113451d0,
+};
+
+static void quirk_amd_nbio_enhanced_atomic(struct pci_dev *host_bridge,
+ const u32 *smn_addrs,
+ size_t nr_smn_addrs)
+{
+ bool changed = false;
+ size_t i;
+ u32 data;
+ int ret;
+
+ for (i = 0; i < nr_smn_addrs; i++) {
+ ret = amd_smn_read(0, smn_addrs[i], &data);
+ if (ret)
+ continue;
+ if (!(data & RX_ENH_ATOMIC_EN))
+ continue;
+ data = data & ~RX_ENH_ATOMIC_EN;
+ ret = amd_smn_write(0, smn_addrs[i], data);
+ if (ret)
+ continue;
+ if (changed)
+ continue;
+ ret = amd_smn_read(0, smn_addrs[i], &data);
+ if (ret)
+ continue;
+ if (data & RX_ENH_ATOMIC_EN)
+ continue;
+ changed = true;
+ }
+
+ if (changed)
+ pci_info(host_bridge, "enhanced atomics disabled\n");
+}
+
+static void quirk_amd_nbio_7_7_disable_enhanced_atomic(struct pci_dev *dev)
+{
+ quirk_amd_nbio_enhanced_atomic(dev, nbio_7_7_pcie_smn_addrs,
+ ARRAY_SIZE(nbio_7_7_pcie_smn_addrs));
+}
+
+static void quirk_amd_nbio_7_11_disable_enhanced_atomic(struct pci_dev *dev)
+{
+ quirk_amd_nbio_enhanced_atomic(dev, nbio_7_11_pcie_smn_addrs,
+ ARRAY_SIZE(nbio_7_11_pcie_smn_addrs));
+}
+
+/* Phoenix, Hawk Point (NBIO 7.7) */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
+ quirk_amd_nbio_7_7_disable_enhanced_atomic);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x14E8,
+ quirk_amd_nbio_7_7_disable_enhanced_atomic);
+
+/* Strix, Krackan, Strix Halo (NBIO 7.11) */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
+ quirk_amd_nbio_7_11_disable_enhanced_atomic);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1507,
+ quirk_amd_nbio_7_11_disable_enhanced_atomic);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
+ quirk_amd_nbio_7_11_disable_enhanced_atomic);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1122,
+ quirk_amd_nbio_7_11_disable_enhanced_atomic);
+
#endif
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] Revert "ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585"
2026-09-08 19:05 [PATCH v2 0/2] Fix for storage corruption w/ AMD IOMMU on 64-bit addressing Mario Limonciello
2026-09-08 19:05 ` [PATCH v2 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports Mario Limonciello
@ 2026-09-08 19:06 ` Mario Limonciello
2026-09-08 19:09 ` sashiko-bot
1 sibling, 1 reply; 5+ messages in thread
From: Mario Limonciello @ 2026-09-08 19:06 UTC (permalink / raw)
To: Bjorn Helgaas, Damien Le Moal, Niklas Cassel
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), H . Peter Anvin,
open list:PCI SUBSYSTEM,
open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
Mario Limonciello, Arthur Husband
This reverts commit 105c42566a550e2d05fc14f763216a8765ee5d0e.
The issue is actually a problem with BIOS configuaration of PCIe
root ports, enabling a feature that causes problems with 64-bit
DMA. It is fixed by adjusting the kernel adjusting the
configuration of those root ports.
Cc: Arthur Husband <artmoty@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/ata/ahci.c | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9b8c0935001cb..bffe50a109b88 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -68,7 +68,6 @@ enum board_ids {
/* board IDs for specific chipsets in alphabetical order */
board_ahci_al,
board_ahci_avn,
- board_ahci_jmb585,
board_ahci_mcp65,
board_ahci_mcp77,
board_ahci_mcp89,
@@ -213,15 +212,6 @@ static const struct ata_port_info ahci_port_info[] = {
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_avn_ops,
},
- /* JMicron JMB582/585: 64-bit DMA is broken, force 32-bit */
- [board_ahci_jmb585] = {
- AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR |
- AHCI_HFLAG_32BIT_ONLY),
- .flags = AHCI_FLAG_COMMON,
- .pio_mask = ATA_PIO4,
- .udma_mask = ATA_UDMA6,
- .port_ops = &ahci_ops,
- },
[board_ahci_mcp65] = {
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
AHCI_HFLAG_YES_NCQ),
@@ -954,14 +944,6 @@ static const struct pci_device_id ahci_pci_tbl[] = {
/* Elkhart Lake AHCI */
PCI_VDEVICE(INTEL, 0x4b63),
.driver_data = board_ahci_pcs_quirk,
- }, {
- /* JMicron JMB582/585: force 32-bit DMA (broken 64-bit implementation) */
- PCI_VDEVICE(JMICRON, 0x0582),
- .driver_data = board_ahci_jmb585,
-
- }, {
- PCI_VDEVICE(JMICRON, 0x0585),
- .driver_data = board_ahci_jmb585,
}, {
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID),
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread