Re: [RFC PATCH v2] PCI: Work around Pericom PI7C9X3G606GPC Port 4 BAR erratum

[sashiko-bot@kernel.org]

> When the Cross-Domain End-Point (CDEP) function is disabled on the
> Pericom PI7C9X3G606GPC, Port 4 exposes neither a BAR resource nor an
> MSI-X capability. It still checks memory requests against
> BAR 0 + 0x7f000 and BAR 0 + 0x7f080, the MSI-X Table and PBA addresses.
> With the internal BAR value at zero, reads reaching Port 4 at these
> addresses receive Unsupported Request (UR) Completions.
> 
> The affected system has this topology:
> 
>   0002:a1:00.0  PI7C9X3G606GPC upstream port [12d8:c008]
>     +-0002:a2:04.0  PI7C9X3G606GPC Port 4 [12d8:c008]
>         +-0002:a3:00.0  Micron 7450 PRO NVMe SSD [1344:51c3]
> 
> Diodes' workaround is to copy the upstream port's BAR 0 into Port 4.
> This places the Table and PBA addresses within MMIO space already
> allocated to the switch. Port 4 accepts the write but still returns
> zero on config-space reads, so readback cannot verify the mirror.
> 
> Firmware can apply the workaround during boot, but Linux BAR sizing
> reads zero from Port 4 and writes that zero back after probing.
> Resource assignment can also move the upstream BAR 0, leaving the
> firmware mirror stale.
> 
> Reapply the mirror after resource assignment and again after PCI
> configuration state is restored during early resume. If the upstream
> BAR is 64-bit, also copy BAR 1 and disable memory decoding while
> updating both halves, unless mmio_always_on is set.
> 
> Assisted-by: Codex:GPT-5
> Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260917103814.1985144-1-nirmoyd@nvidia.com?part=1