From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Jingoo Han <jingoohan1@gmail.com>,
Manivannan Sadhasivam <mani@kernel.org>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
"Krzysztof Wilczynski" <kwilczynski@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>, <linux-pci@vger.kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Vidya Sagar <vidyas@nvidia.com>,
Niklas Cassel <cassel@kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields
Date: Wed, 23 Sep 2026 12:47:06 +0530 [thread overview]
Message-ID: <20260923071706.1134320-6-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20260923071706.1134320-1-mmaddireddy@nvidia.com>
Use the shared DesignWare RAS-DES event counter register offsets and
field masks in the common debugfs code instead of carrying duplicate
private definitions.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
.../controller/dwc/pcie-designware-debugfs.c | 56 +++++++++++--------
drivers/pci/controller/dwc/pcie-designware.h | 1 -
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
index be0b84665c9e..daabc6ff0d85 100644
--- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
+++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
@@ -31,14 +31,8 @@
#define ERR_INJ_ENABLE_REG 0x30
-#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc
-
-#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8
-#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24)
-#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16)
#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8)
#define EVENT_COUNTER_STATUS BIT(7)
-#define EVENT_COUNTER_ENABLE GENMASK(4, 2)
#define PER_EVENT_ON 0x3
#define PER_EVENT_OFF 0x1
@@ -356,11 +350,15 @@ static void set_event_number(struct dwc_pcie_rasdes_priv *pdata,
{
u32 val;
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
- val &= ~EVENT_COUNTER_ENABLE;
- FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no);
- FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no);
- dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
+ val &= ~EVENT_COUNTER_ENABLE_MASK;
+ FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val,
+ event_list[pdata->idx].group_no);
+ FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val,
+ event_list[pdata->idx].event_no);
+ dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
}
static ssize_t counter_enable_read(struct file *file, char __user *buf,
@@ -375,13 +373,16 @@ static ssize_t counter_enable_read(struct file *file, char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
mutex_unlock(&rinfo->reg_event_lock);
val = FIELD_GET(EVENT_COUNTER_STATUS, val);
if (val)
- pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n");
+ pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX,
+ "Counter Enabled\n");
else
- pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n");
+ pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX,
+ "Counter Disabled\n");
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
}
@@ -401,13 +402,15 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
if (enable)
- val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON);
+ val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_ON);
else
- val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF);
+ val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_OFF);
- dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
+ dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
/*
* While enabling the counter, always read the status back to check if
@@ -416,7 +419,7 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf,
*/
if (enable) {
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
- RAS_DES_EVENT_COUNTER_CTRL_REG);
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) {
mutex_unlock(&rinfo->reg_event_lock);
return -EOPNOTSUPP;
@@ -440,7 +443,8 @@ static ssize_t counter_lane_read(struct file *file, char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
mutex_unlock(&rinfo->reg_event_lock);
val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val);
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val);
@@ -463,9 +467,11 @@ static ssize_t counter_lane_write(struct file *file, const char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane);
- dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
+ dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
mutex_unlock(&rinfo->reg_event_lock);
return count;
@@ -483,9 +489,11 @@ static ssize_t counter_value_read(struct file *file, char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_DATA);
mutex_unlock(&rinfo->reg_event_lock);
- pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val);
+ pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX,
+ "Counter value: %d\n", val);
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index f70b7da97e07..4d55339750f0 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -276,7 +276,6 @@
#define EVENT_COUNTER_ENABLE_ALL 0x7
#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2)
#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16)
-#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
#define EVENT_COUNTER_EVENT_L1 0x5
--
2.34.1
next prev parent reply other threads:[~2026-09-23 7:19 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
2026-09-23 7:23 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
2026-09-23 7:31 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 3/5] PCI: dwc: Drop unused shift macros Manikanta Maddireddy
2026-09-23 7:28 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
2026-09-23 7:29 ` sashiko-bot
2026-09-23 7:17 ` Manikanta Maddireddy [this message]
2026-09-23 7:34 ` [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields sashiko-bot
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