From: sashiko-bot@kernel.org
To: "Manikanta Maddireddy" <mmaddireddy@nvidia.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields
Date: Wed, 23 Sep 2026 07:34:54 +0000 [thread overview]
Message-ID: <20260923073454.EE1971F0089C@smtp.kernel.org> (raw)
In-Reply-To: <20260923071706.1134320-6-mmaddireddy@nvidia.com>
> Use the shared DesignWare RAS-DES event counter register offsets and
> field masks in the common debugfs code instead of carrying duplicate
> private definitions.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923071706.1134320-1-mmaddireddy@nvidia.com?part=5
prev parent reply other threads:[~2026-09-23 7:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
2026-09-23 7:23 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
2026-09-23 7:31 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 3/5] PCI: dwc: Drop unused shift macros Manikanta Maddireddy
2026-09-23 7:28 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
2026-09-23 7:29 ` sashiko-bot
2026-09-23 7:17 ` [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Manikanta Maddireddy
2026-09-23 7:34 ` sashiko-bot [this message]
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