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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Richard Cheng <icheng@nvidia.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration
Date: Tue, 1 Sep 2026 19:23:44 -0700	[thread overview]
Message-ID: <2a786888-171e-497b-beac-a16cb2ca3420@nvidia.com> (raw)
In-Reply-To: <aoKa7RILK51ZkpHs@MWDK4CY14F>

On 8/16/26 10:30 PM, Richard Cheng wrote:
>> +	rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> Hi Srirangan,
> 
> I can't compile successfully after your patch series applied, I think the
> issue is here.
> 
> With CONFIG_CXL_BUS=y or CONFIG_CXL_BUS=m alone with
> """
> $ make -j $(nproc) vmlinux modules
> """
> 
> The build fails with:
> 
> """
>      drivers/cxl/core/resource.c:501:38: error:
>        ‘CXL_REGLOC_RBI_COMPONENT’ undeclared
>      drivers/cxl/core/resource.c:501:38: error:
>        type of formal parameter 2 is incomplete
> """
> 
> drivers/cxl/cxl.h only forward-declares enum cxl_regloc_type.
> CXL_REFLOC_RBI_COMPONENT and the complete enum def are provided
> by include/cxl/pci.h
> 
> I add the following header so we can include drivers/cxl/core/resource.c
> to fix the failure.
> 
> """
> #include <cxl/pci.h>
> """
> 
> Best regards,
> Richard Cheng.
Hi Richard,

Thanks for the report. v10 was based on v7.2-rc2 (8cdeaa50eae8), where 
patch 5 includes <cxlpci.h>. On that base, drivers/cxl/cxlpci.h provides 
the complete enum cxl_regloc_type definition and CXL_REGLOC_RBI_COMPONENT.

The definitions moved to <cxl/pci.h> in the newer tree as part of the 
CXL Type 2 enabling work. v11 is rebased onto v7.3-rc1 and uses the new 
public header.

If this failure reproduces on the declared v10 base, please let me know. 
Otherwise, I guess this resulted from applying v10 to a newer base after 
the header relocation?
But anyways, in v11, patches should use the new base and compile 
individually.

-- 
Regards,
Srirangan

  reply	other threads:[~2026-09-02  2:23 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04 19:29 [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 01/12] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-08-04 19:46   ` sashiko-bot
2026-08-05  2:13   ` Alison Schofield
2026-09-02  0:52     ` Srirangan Madhavan
2026-08-20 21:13   ` Dave Jiang
2026-08-24  7:11   ` Li Ming
2026-08-24  7:19     ` Li Ming
2026-09-02  1:18       ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 02/12] cxl: Pass decoder settings to HDM commit helpers Srirangan Madhavan
2026-08-04 19:49   ` sashiko-bot
2026-08-20 22:21   ` Dave Jiang
2026-09-02  1:51     ` Srirangan Madhavan
2026-08-24  7:33   ` Li Ming
2026-09-02  1:53     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 03/12] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-08-04 19:45   ` sashiko-bot
2026-08-20 23:25   ` Dave Jiang
2026-09-02  1:58     ` Srirangan Madhavan
2026-09-02  2:06     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 04/12] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-08-04 19:40   ` sashiko-bot
2026-08-21 22:12   ` Dave Jiang
2026-09-02  2:12     ` Srirangan Madhavan
2026-08-24  7:53   ` Li Ming
2026-09-02  2:13     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-08-04 19:51   ` sashiko-bot
2026-08-05  2:28   ` Alison Schofield
2026-09-02  2:14     ` Srirangan Madhavan
2026-08-17  5:30   ` Richard Cheng
2026-09-02  2:23     ` Srirangan Madhavan [this message]
2026-08-21 23:33   ` Dave Jiang
2026-09-02  2:30     ` Srirangan Madhavan
2026-08-25  6:58   ` Li Ming
2026-09-02  2:48     ` Srirangan Madhavan
2026-08-26 18:30   ` Lucero Palau, Alejandro
2026-09-02  3:22     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 06/12] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-08-04 19:42   ` sashiko-bot
2026-08-24 22:24   ` Dave Jiang
2026-08-26 18:09   ` Lucero Palau, Alejandro
2026-09-02  3:52     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 07/12] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-08-04 19:38   ` sashiko-bot
2026-08-25 20:30   ` Dave Jiang
2026-09-02  4:39     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 08/12] cxl: Reject CXL Reset on multifunction devices Srirangan Madhavan
2026-08-04 19:40   ` sashiko-bot
2026-08-25 20:32   ` Dave Jiang
2026-08-26 18:47   ` Lucero Palau, Alejandro
2026-09-02  4:52     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 09/12] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-08-04 19:44   ` sashiko-bot
2026-08-17  7:12   ` Richard Cheng
2026-09-02  5:17     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 10/12] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-08-04 20:00   ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 11/12] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-08-04 19:41   ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 12/12] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-08-04 19:59   ` sashiko-bot
2026-08-13  9:35 ` [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Alejandro Lucero Palau
2026-08-25 21:13 ` Dave Jiang
2026-09-02  5:11   ` Srirangan Madhavan

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