From: Srirangan Madhavan <smadhavan@nvidia.com>
To: "Lucero Palau, Alejandro" <alejandro.lucero-palau@amd.com>,
Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration
Date: Tue, 1 Sep 2026 20:22:14 -0700 [thread overview]
Message-ID: <4b3c1052-c071-446e-9c40-7db11d30104e@nvidia.com> (raw)
In-Reply-To: <cf670fd8-008b-45f9-9edb-f0fdfde83666@amd.com>
On 8/26/26 11:30 AM, Lucero Palau, Alejandro wrote:
>> + up_read(&cxl_rwsem.dpa);
>> + return 0;
>> + }
>
>
> Why to release the lock here? or why is this needed at all?
>
>
> If I understand this correctly, this is happening before the cxl core
> does any sort of initialization, indeed, the potential pdev driver can
> not be probed either, that seems to be the reason here, to get the HDM
> data if committed for doing the reset before the driver binds. Who could
> be setting pdev->hdm?
>
>
> I can not see the necessity and if I'm right, you can avoid the
> pdev->hdm check as well at the end and avoid the call for releasing
> info. Another comment below.
>
Hi Alejandro,
Yes, that is the intent: capture committed HDM state during PCI
enumeration so it is available to reset paths before a driver binds.
pdev->hdm may already have been populated by the call from
pci_bus_add_device() when the fallback call from CXL core enumeration
runs. The initial check makes that later call a no-op. Since the lock is
released during allocation and MMIO access, the final check protects the
check-then-publish window if the two
call sites overlap.
>
>> + up_read(&cxl_rwsem.dpa);
>> +
>> + rc = cxl_pci_hdm_capable(pdev);
>> + if (rc)
>> + return rc;
>> +
>> + rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
>> + if (rc)
>> + return rc;
snip
>> + rc = rc2;
>> + }
>> + }
>> +
>> + if (rc)
>> + goto out_free_info;
>> +
>> + down_write(&cxl_rwsem.dpa);
>> + if (!pdev->hdm) {
>> + pdev->hdm = info;
>> + info = NULL;
>> + }
>> + up_write(&cxl_rwsem.dpa);
>> +
>> + cxl_pci_hdm_info_free(info);
>
>
> This seems weird if info is being assigned above to the pdev. Maybe it
> would be clearer if done in an else branch instead:
>
> down_write(&cxl_rwsem.dpa);
> if (!pdev->hdm) {
> pdev->hdm = info;
> info = NULL;
> } else {
> cxl_pci_hdm_info_free(info);
> }
> up_write(&cxl_rwsem.dpa);
>
> Thanks,
>
> Alejandro.
In v11, I converted both lock regions to scoped guards and followed your
suggestion to free the newly allocated duplicate explicitly in the else
branch.
--
Regards,
Srirangan
next prev parent reply other threads:[~2026-09-02 3:22 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-04 19:29 [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 01/12] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-08-04 19:46 ` sashiko-bot
2026-08-05 2:13 ` Alison Schofield
2026-09-02 0:52 ` Srirangan Madhavan
2026-08-20 21:13 ` Dave Jiang
2026-08-24 7:11 ` Li Ming
2026-08-24 7:19 ` Li Ming
2026-09-02 1:18 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 02/12] cxl: Pass decoder settings to HDM commit helpers Srirangan Madhavan
2026-08-04 19:49 ` sashiko-bot
2026-08-20 22:21 ` Dave Jiang
2026-09-02 1:51 ` Srirangan Madhavan
2026-08-24 7:33 ` Li Ming
2026-09-02 1:53 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 03/12] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-08-04 19:45 ` sashiko-bot
2026-08-20 23:25 ` Dave Jiang
2026-09-02 1:58 ` Srirangan Madhavan
2026-09-02 2:06 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 04/12] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-08-04 19:40 ` sashiko-bot
2026-08-21 22:12 ` Dave Jiang
2026-09-02 2:12 ` Srirangan Madhavan
2026-08-24 7:53 ` Li Ming
2026-09-02 2:13 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-08-04 19:51 ` sashiko-bot
2026-08-05 2:28 ` Alison Schofield
2026-09-02 2:14 ` Srirangan Madhavan
2026-08-17 5:30 ` Richard Cheng
2026-09-02 2:23 ` Srirangan Madhavan
2026-08-21 23:33 ` Dave Jiang
2026-09-02 2:30 ` Srirangan Madhavan
2026-08-25 6:58 ` Li Ming
2026-09-02 2:48 ` Srirangan Madhavan
2026-08-26 18:30 ` Lucero Palau, Alejandro
2026-09-02 3:22 ` Srirangan Madhavan [this message]
2026-08-04 19:29 ` [PATCH v10 06/12] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-08-04 19:42 ` sashiko-bot
2026-08-24 22:24 ` Dave Jiang
2026-08-26 18:09 ` Lucero Palau, Alejandro
2026-09-02 3:52 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 07/12] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-08-04 19:38 ` sashiko-bot
2026-08-25 20:30 ` Dave Jiang
2026-09-02 4:39 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 08/12] cxl: Reject CXL Reset on multifunction devices Srirangan Madhavan
2026-08-04 19:40 ` sashiko-bot
2026-08-25 20:32 ` Dave Jiang
2026-08-26 18:47 ` Lucero Palau, Alejandro
2026-09-02 4:52 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 09/12] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-08-04 19:44 ` sashiko-bot
2026-08-17 7:12 ` Richard Cheng
2026-09-02 5:17 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 10/12] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-08-04 20:00 ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 11/12] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-08-04 19:41 ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 12/12] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-08-04 19:59 ` sashiko-bot
2026-08-13 9:35 ` [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Alejandro Lucero Palau
2026-08-25 21:13 ` Dave Jiang
2026-09-02 5:11 ` Srirangan Madhavan
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