Re: [PATCH] PCI/AER: Consolidate CXL and native AER reporting paths

[Karolina Stolarek <karolina.stolarek@oracle.com>]

[+Jonathan to ask about CXL error injection in qemu]

On 21/03/2025 16:06, Bjorn Helgaas wrote:
> On Fri, Mar 21, 2025 at 02:56:16PM +0100, Karolina Stolarek wrote:
>>
>> ... But still, the question is if going with the
>> new format that matches what's in AER a bad or disruptive thing. I'd like to
>> try going in the direction of using one way of reporting AER errors, if
>> possible.
> 
> Absolutely, I agree 100%.  The choice between native AER and GHES is
> made by the platform, not by the OS, so I think it's crazy that we log
> them differently.  We just need to include information about any log
> format changes we make to help users adapt to them.

I agree, we should highlight the difference. I'm trying to get 
before-after logs for CXL but I can't get this to work on pci-next 
kernel (i.e., without Terry's patchset).

Jonathan, I'm sorry for dragging you into the thread, but I thought you 
could provide suggestions on what might be wrong with my setup.

I tried to test this patch by injecting a CXL Correctable Error via 
QMP[0], following these instructions[1]. 
qmp_cxl_inject_correctable_error() finishes with no issues (it calls 
pcie_aer_inject_error()) but I see no AER log or whatsoever. This is the 
command that I used[2], with QEMU v7.1.0-rc2-21892-gd9a4282c4b and the 
pci-next kernel.

Is there something else I need to enable or provide some parameters to 
get this working?

All the best,
Karolina

------------------------------------------------------------------------
[0]:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-correctable-error",
     "arguments": {
         "path": "/machine/peripheral/cxl-vmem0",
         "type": "physical"
     }
}

[1] - 
https://gitlab.com/jic23/qemu/-/commit/b3488ff7ee6ebfe247c9af751f44f2990babd4a7

[2]:
$ qemu-system-x86_64 -enable-kvm -cpu host -smp 4 -m 16G -rtc base=utc \
   -M q35,cxl=on -nographic -serial mon:stdio \
   -drive 
file=/.../ovmf_code.pure-efi.fd,index=0,if=pflash,format=raw,readonly=on \
   -drive file=/.../ovmf-vars.base_image.fd,index=1,if=pflash,format=raw \
   -object 
memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M 
\
   -object 
memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa0.raw,size=256M \
   -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
   -device cxl-rp,port=0,bus=cxl.1,id=root_port0,chassis=0,slot=0 \
   -device cxl-upstream,bus=root_port0,id=us0 \
   -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \
   -device 
cxl-type3,bus=swport0,volatile-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-vmem0 \
   -qmp tcp:localhost:4444,server,wait=off \
   -M 
cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k 
\
   -hda disk1.qcow2