Re: [RFC PATCH] pciehp: Wait for link get trained in pci_check_link_status()

Re: [RFC PATCH] pciehp: Wait for link get trained in pci_check_link_status()

[Kenji Kaneshige]

(2011/11/09 6:54), Yinghai Lu wrote:
> On 11/08/2011 07:27 AM, Yinghai Lu wrote:
>
>> On 11/08/2011 01:19 AM, Kenji Kaneshige wrote:
>>>
>>> What about the patch below? I think it's much simpler and has less impact.
>>
>> Should work. will try it today.
>
>
> yes, that works too.
>
> Thanks
>
> Yinghai
>

I updated the patch with description. I split it into two and
a logic is a little changed. Could you check these?

Regards,
Kenji Kaneshige

[PATCH 1/2] pciehp: wait 1000 ms before Link Training check

[Kenji Kaneshige]

We need to wait for 1000 ms after Data Link Layer Link Active (DLLLA)
bit reads 1b before sending configuration request. Currently pciehp
does this wait after checking Link Training (LT) bit. But we need it
before checking LT bit because LT is still set even after DLLLA bit is
set on some platforms.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
---
 drivers/pci/hotplug/pciehp_ctrl.c |    3 ---
 drivers/pci/hotplug/pciehp_hpc.c  |    8 ++++++++
 2 files changed, 8 insertions(+), 3 deletions(-)

Index: linux-3.1/drivers/pci/hotplug/pciehp_ctrl.c
===================================================================
--- linux-3.1.orig/drivers/pci/hotplug/pciehp_ctrl.c
+++ linux-3.1/drivers/pci/hotplug/pciehp_ctrl.c
@@ -213,9 +213,6 @@ static int board_added(struct slot *p_sl
 		goto err_exit;
 	}
 
-	/* Wait for 1 second after checking link training status */
-	msleep(1000);
-
 	/* Check for a power fault */
 	if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
 		ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
Index: linux-3.1/drivers/pci/hotplug/pciehp_hpc.c
===================================================================
--- linux-3.1.orig/drivers/pci/hotplug/pciehp_hpc.c
+++ linux-3.1/drivers/pci/hotplug/pciehp_hpc.c
@@ -280,6 +280,14 @@ int pciehp_check_link_status(struct cont
         else
                 msleep(1000);
 
+	/*
+	 * Need to wait for 1000 ms after Data Link Layer Link Active
+	 * (DLLLA) bit reads 1b before sending configuration request.
+	 * We need it before checking Link Training (LT) bit becuase
+	 * LT is still set even after DLLLA bit is set on some platform.
+	 */
+	msleep(1000);
+
 	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 	if (retval) {
 		ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");

[PATCH 2/2] pciehp: wait 100 ms after Link Training check

[Kenji Kaneshige]

If the port supports Link speeds greater than 5.0 GT/s, we must wait
for 100 ms after Link training completes before sending configuration
request.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
---
 drivers/pci/hotplug/pciehp_hpc.c |    8 ++++++++
 1 file changed, 8 insertions(+)

Index: linux-3.1/drivers/pci/hotplug/pciehp_hpc.c
===================================================================
--- linux-3.1.orig/drivers/pci/hotplug/pciehp_hpc.c
+++ linux-3.1/drivers/pci/hotplug/pciehp_hpc.c
@@ -302,6 +302,14 @@ int pciehp_check_link_status(struct cont
 		return retval;
 	}
 
+	/*
+	 * If the port supports Link speeds greater than 5.0 GT/s, we
+	 * must wait for 100 ms after Link training completes before
+	 * sending configuration request.
+	 */
+	if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT)
+		msleep(100);
+
 	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 
 	return retval;

Re: [PATCH 1/2] pciehp: wait 1000 ms before Link Training check

[Yinghai Lu]

On 11/09/2011 11:40 PM, Kenji Kaneshige wrote:

> We need to wait for 1000 ms after Data Link Layer Link Active (DLLLA)
> bit reads 1b before sending configuration request. Currently pciehp
> does this wait after checking Link Training (LT) bit. But we need it
> before checking LT bit because LT is still set even after DLLLA bit is
> set on some platforms.
> 
> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>


Acked-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Yinghai Lu <yinghai@kernel.org>

Re: [PATCH 2/2] pciehp: wait 100 ms after Link Training check

[Yinghai Lu]

On 11/09/2011 11:42 PM, Kenji Kaneshige wrote:

> If the port supports Link speeds greater than 5.0 GT/s, we must wait
> for 100 ms after Link training completes before sending configuration
> request.
> 
> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>



Acked-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Yinghai Lu <yinghai@kernel.org>

Re: [PATCH 2/2] pciehp: wait 100 ms after Link Training check

[Jesse Barnes]

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On Thu, 10 Nov 2011 11:10:56 -0800
Yinghai Lu <yinghai.lu@oracle.com> wrote:

> On 11/09/2011 11:42 PM, Kenji Kaneshige wrote:
> 
> > If the port supports Link speeds greater than 5.0 GT/s, we must wait
> > for 100 ms after Link training completes before sending configuration
> > request.
> > 
> > Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
> 
> 
> 
> Acked-by: Yinghai Lu <yinghai@kernel.org>
> Tested-by: Yinghai Lu <yinghai@kernel.org>

Applied these two to my for-linus branch, thanks guys.

-- 
Jesse Barnes, Intel Open Source Technology Center

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Re: [PATCH 2/2] pciehp: wait 100 ms after Link Training check

[Yinghai Lu]

On 11/11/2011 09:32 AM, Jesse Barnes wrote:

> On Thu, 10 Nov 2011 11:10:56 -0800
> Yinghai Lu <yinghai.lu@oracle.com> wrote:
> 
>> On 11/09/2011 11:42 PM, Kenji Kaneshige wrote:
>>
>>> If the port supports Link speeds greater than 5.0 GT/s, we must wait
>>> for 100 ms after Link training completes before sending configuration
>>> request.
>>>
>>> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
>>
>>
>>
>> Acked-by: Yinghai Lu <yinghai@kernel.org>
>> Tested-by: Yinghai Lu <yinghai@kernel.org>
> 
> Applied these two to my for-linus branch, thanks guys.
> 


Thanks, We may need to put them into stable too.

Yinghai

Re: [PATCH 2/2] pciehp: wait 100 ms after Link Training check

[Greg KH]

On Fri, Nov 11, 2011 at 09:33:32AM -0800, Yinghai Lu wrote:
> On 11/11/2011 09:32 AM, Jesse Barnes wrote:
> 
> > On Thu, 10 Nov 2011 11:10:56 -0800
> > Yinghai Lu <yinghai.lu@oracle.com> wrote:
> > 
> >> On 11/09/2011 11:42 PM, Kenji Kaneshige wrote:
> >>
> >>> If the port supports Link speeds greater than 5.0 GT/s, we must wait
> >>> for 100 ms after Link training completes before sending configuration
> >>> request.
> >>>
> >>> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
> >>
> >>
> >>
> >> Acked-by: Yinghai Lu <yinghai@kernel.org>
> >> Tested-by: Yinghai Lu <yinghai@kernel.org>
> > 
> > Applied these two to my for-linus branch, thanks guys.
> > 
> 
> 
> Thanks, We may need to put them into stable too.

Then send stable@vger.kernel.org the git commit ids once they show up in
Linus's tree.

thanks,

greg k-h

Re: pciehp for stable

[Greg KH]

On Wed, Nov 23, 2011 at 06:03:46PM -0800, Yinghai Lu wrote:
> On 11/11/2011 09:40 AM, Greg KH wrote:
> 
> >> Thanks, We may need to put them into stable too.
> > 
> > Then send stable@vger.kernel.org the git commit ids once they show up in
> > Linus's tree.
> > 
> 
> 
> >From 0027cb3e1947d0f453fece40ed16764fb362bac6 Mon Sep 17 00:00:00 2001
> From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
> Date: Thu, 10 Nov 2011 16:40:37 +0900
> Subject: [PATCH] PCI: pciehp: wait 1000 ms before Link Training check
> 
> 
> >From b3c004542229099e18198061c737e13eafc8d4d6 Mon Sep 17 00:00:00 2001
> From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
> Date: Thu, 10 Nov 2011 16:42:16 +0900
> Subject: [PATCH] PCI: pciehp: wait 100 ms after Link Training check

Are you sure these patches are correct?  Linus complained about them,
and I will to :)

Please get Jesse to ack them and I'll apply them.

thanks,

greg k-h

Re: pciehp for stable

[Greg KH]

On Sat, Nov 26, 2011 at 07:25:44PM -0800, Greg KH wrote:
> On Wed, Nov 23, 2011 at 06:03:46PM -0800, Yinghai Lu wrote:
> > On 11/11/2011 09:40 AM, Greg KH wrote:
> > 
> > >> Thanks, We may need to put them into stable too.
> > > 
> > > Then send stable@vger.kernel.org the git commit ids once they show up in
> > > Linus's tree.
> > > 
> > 
> > 
> > >From 0027cb3e1947d0f453fece40ed16764fb362bac6 Mon Sep 17 00:00:00 2001
> > From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
> > Date: Thu, 10 Nov 2011 16:40:37 +0900
> > Subject: [PATCH] PCI: pciehp: wait 1000 ms before Link Training check
> > 
> > 
> > >From b3c004542229099e18198061c737e13eafc8d4d6 Mon Sep 17 00:00:00 2001
> > From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
> > Date: Thu, 10 Nov 2011 16:42:16 +0900
> > Subject: [PATCH] PCI: pciehp: wait 100 ms after Link Training check
> 
> Are you sure these patches are correct?  Linus complained about them,
> and I will to :)
> 
> Please get Jesse to ack them and I'll apply them.

As I have gotten no reply in the week since I sent this, I'm dropping
this request from my queue, sorry.

greg k-h