Linux PCI subsystem development
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From: Sathyanarayanan Kuppuswamy  <sathyanarayanan.kuppuswamy@linux.intel.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
	oohall@gmail.com, Lukas Wunner <lukas@wunner.de>,
	Chris Chiu <chris.chiu@canonical.com>,
	Ashok Raj <ashok.raj@intel.com>,
	Sheng Bi <windy.bi.enflame@gmail.com>,
	Ravi Kishore Koppuravuri <ravi.kishore.koppuravuri@intel.com>,
	Stanislav Spassov <stanspas@amazon.de>,
	Yang Su <yang.su@linux.alibaba.com>,
	shuo.tan@linux.alibaba.com, linux-pci@vger.kernel.org
Subject: Re: [PATCH v3] PCI/PM: Bail out early in pci_bridge_wait_for_secondary_bus() if link is not trained
Date: Thu, 13 Apr 2023 07:16:46 -0700	[thread overview]
Message-ID: <4a294f9d-6395-b8de-eb36-46c636876c8e@linux.intel.com> (raw)
In-Reply-To: <20230413101642.8724-1-mika.westerberg@linux.intel.com>



On 4/13/23 3:16 AM, Mika Westerberg wrote:
> If the Root/Downstream Port supports active link reporting we can check
> if the link is trained before waiting for the device to respond. If the
> link is not trained, there is no point waiting for the whole ~60s so
> bail out early in that case.
> 
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---

Looks good to me.

Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

> As discussed in the email thread of the previous version here:
> 
>   https://lore.kernel.org/linux-pci/20230404052714.51315-1-mika.westerberg@linux.intel.com/
> 
> This adds the last change on top of
> 
>   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=reset
> 
> 
>  drivers/pci/pci.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 0b4f3b08f780..61bf8a4b2099 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5037,6 +5037,22 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
>  		}
>  	}
>  
> +	/*
> +	 * Everything above is handling the delays mandated by the PCIe r6.0
> +	 * sec 6.6.1.
> +	 *
> +	 * If the port supports active link reporting we now check one more
> +	 * time if the link is active and if not bail out early with the
> +	 * assumption that the device is not present anymore.
> +	 */
> +	if (dev->link_active_reporting) {
> +		u16 status;
> +
> +		pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status);
> +		if (!(status & PCI_EXP_LNKSTA_DLLLA))
> +			return -ENOTTY;
> +	}
> +
>  	return pci_dev_wait(child, reset_type,
>  			    PCIE_RESET_READY_POLL_MS - delay);
>  }

-- 
Sathyanarayanan Kuppuswamy
Linux Kernel Developer

  reply	other threads:[~2023-04-13 14:25 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-13 10:16 [PATCH v3] PCI/PM: Bail out early in pci_bridge_wait_for_secondary_bus() if link is not trained Mika Westerberg
2023-04-13 14:16 ` Sathyanarayanan Kuppuswamy [this message]
2023-04-14  7:42 ` Lukas Wunner
2023-04-14 10:11   ` Mika Westerberg
2023-04-16  7:48     ` Lukas Wunner
2023-04-17  6:07       ` Mika Westerberg

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