Re: [PATCH 07/11] PCI: Add PCIe Device 3 Extended Capability enumeration

[Dan Williams <dan.j.williams@intel.com>]

Dan Williams wrote:
> Ilpo Järvinen wrote:
> > On Thu, 5 Dec 2024, Dan Williams wrote:
> > 
> > > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure,
> > > enumerates new link capabilities and status added for Gen 6 devices. One
> > > of the link details enumerated in that register block is the "Segment
> > > Captured" status in the Device Status 3 register. That status is
> > > relevant for enabling IDE (Integrity & Data Encryption) whereby
> > > Selective IDE streams can be limited to a given requester id range
> > > within a given segment.
> > > 
> > > If a device has captured its Segment value then it knows that PCIe Flit
> > > Mode is enabled via all links in the path that a configuration write
> > > traversed. IDE establishment requires that "Segment Base" in
> > > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be
> > > programmed if the RID association mechanism is in effect.
> > > 
> > > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to
> > > setup the segment base when using the RID association facility, but no
> > > known deployments today depend on this.
> > > 
> > > Cc: Lukas Wunner <lukas@wunner.de>
> > > Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > Cc: Samuel Ortiz <sameo@rivosinc.com>
> > > Cc: Alexey Kardashevskiy <aik@amd.com>
> > > Cc: Xu Yilun <yilun.xu@linux.intel.com>
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> [..]
> > > @@ -1210,6 +1211,12 @@
> > >  #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL		0x00ff0000
> > >  #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX	0xff000000
> > >  
> > > +/* Device 3 Extended Capability */
> > > +#define PCI_DEV3_CAP		0x4	/* Device 3 Capabilities Register */
> > > +#define PCI_DEV3_CTL		0x8	/* Device 3 Control Register */
> > 
> > Should save/restore too be added for DEV3_CTL?
> 
> Good point, yes it should.

...although only when the kernel adds a use case to write to DEV3_CTL,
for now the use case is read-only for DEV3_CAP.