Re: RFC about how to obtain PCIE TPH steer-tag on ARM64 platform

[fengchengwen <fengchengwen@huawei.com>]

On 1/15/2026 12:36 AM, Wei Huang wrote:
> On Wed, Jan 14, 2026 at 11:52:50AM +0800, fengchengwen wrote:
>> On 1/14/2026 6:38 AM, Wei Huang wrote:
>>> On Tue, Jan 13, 2026 at 01:07:13PM -0600, Bjorn Helgaas wrote:
>>>> On Mon, Jan 12, 2026 at 11:01:31AM +0800, fengchengwen wrote:
>>>>> Hi all,
>>>>>
>>>>> We want to enable PCIE TPH feature on ARM64 platform, but we encounter the
>>>>> following problem:
>>>>>
>>>>> 1. The pcie_tph_get_cpu_st() function invokes the ACPI DSM method to
>>>>>    obtain the steer-tag of the CPU. According to the definition of
>>>>>    the DSM method [1], the cpu_uid should be "ACPI processor uid".
>>>>
>>>>> 2. In the current implementation, the ACPI DSM method is invoked
>>>>>    directly using the logical core number, which works on the x86
>>>>>    platform but does not work on the ARM64 platform because the
>>>>>    logical core ID is not the same as the ACPI processor ID when the
>>>>>    PG exists.
>>>>
>>>> PG?
>>>>
>>>>> Because the ARM64 platform generates steer-tag based on the MPIDR
>>>>> information (at least for the Kunpeng platform). Therefore, we have
>>>>> two option:
>>>>>
>>>>> Option-1: convert logic core ID to ACPI process ID: use
>>>>>           get_acpi_id_for_cpu() to get ACPI process ID in
>>>>>           pcie_tph_get_cpu_st() before invoke dsm [2], and BIOS/ACPI
>>>>>           use process ID to get corresponding MPIDR, and then
>>>>>           generate steer-tag from MPIDR.
>>>
>>> In my opinion, if this is achievable in your BIOS/ACPI, it is clean vs. Option-2 and preferred.
>>
>> Yes, it's achievable for out BIOS/ACPI, and we will adopt this option.
>>
>>>
>>>>>
>>>>> Option-2: convert logic core ID to MPIDR: use cpu_logical_map() to
>>>>>           get MPIDR in pcie_tph_get_cpu_st() before invoke dsm, and
>>>>>           BIOS/ACPI use it to generate steer-tag directly.
>>>
>>> This solution requires you to change the ECN and ratify it (as suggested by Bjorn below). The implementation can also be complicated.
>>
>> Indeed, and it may take a long time.
>>
>> @Wei, I have another question:
>> The cache is hierarchical, for example, L2 or L3. Does the DSM mode support the specified cache level?
>> I checked the ECN doc and there are "Cache Reference" fields, but the kernel code don't enable them.
> 
> ECN does provide the "Cache Reference" field as part of argument2. Our platforms don't use it and don't plan to use it soon. You can explore the use cases if your platforms need it.
> 
> I want to point out that PCIe TLP header doesn't have a field for cache level. So no matter what, TLP header will stuck with 8- or 16-bit STs.

Okay, I will try to understand how to use "Cache Reference" as cache level parameter.
I think this would give the user a more refined ability.

> 
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> 
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