Re: [PATCH] PCI/DPC: Yet another quirk for PIO log size on Intel Raptor Lake-P

[Takashi Iwai <tiwai@suse.de>]

On Sun, 05 Jan 2025 09:25:20 +0100,
Mika Westerberg wrote:
> 
> Hi,
> 
> On Fri, Jan 03, 2025 at 04:53:15PM -0600, Bjorn Helgaas wrote:
> > On Thu, Jan 02, 2025 at 05:43:13PM +0100, Takashi Iwai wrote:
> > > There is yet another PCI entry for Intel Raptor Lake-P that shows the
> > >   error "DPC: RP PIO log size 0 is invalid":
> > >   0000:00:07.0 PCI bridge [0604]: Intel Corporation Raptor Lake-P Thunderbolt 4 PCI Express Root Port #0 [8086:a76e]
> > >   0000:00:07.2 PCI bridge [0604]: Intel Corporation Raptor Lake-P Thunderbolt 4 PCI Express Root Port #2 [8086:a72f]
> > > 
> > > Add the corresponding quirk entry for 8086:a72f.
> > > 
> > > Note that the one for 8086:a76e has been already added by the commit
> > > 627c6db20703 ("PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root
> > > Ports").
> > 
> > Intel folks, what's the long-term resolution of this?  I'm kind of
> > tired of adding quirks like this.  So far we have these (not including
> > the current patch), dating back to Aug 2022:
> > 
> >   627c6db20703 ("PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports")
> >   3b8803494a06 ("PCI/DPC: Quirk PIO log size for Intel Ice Lake Root Ports")
> >   5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root Ports")
> > 
> > I *thought* this problem was caused by BIOS defects that were supposed
> > to be fixed, but nothing seems to be happening.
> 
> As far as I know it should be fixed already. I just checked my MTLP and PTL
> systems (both with integrated TBT PCIe root ports) and I don't see the
> message anymore. I don't have RPL system though. This is on reference
> hardware and BIOS so it is possible that the fix has not been taken into
> the OEM BIOS.

The reporter verified that the issue persists with the latest BIOS.
Sigh.


Takashi