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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Maciej W. Rozycki" <macro@orcam.me.uk>,
	"Lukas Wunner" <lukas@wunner.de>,
	"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
	"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
	"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	linux-pm@vger.kernel.org,
	"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Amit Kucheria" <amitk@kernel.org>,
	"Zhang Rui" <rui.zhang@intel.com>,
	"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>
Subject: Re: [PATCH v8 1/8] PCI: Protect Link Control 2 Register with RMW locking
Date: Thu, 17 Oct 2024 13:30:00 +0300 (EEST)	[thread overview]
Message-ID: <8b022694-ed39-5216-67ed-f532ecb576df@linux.intel.com> (raw)
In-Reply-To: <20241017111213.00005d4f@Huawei.com>

[-- Attachment #1: Type: text/plain, Size: 2958 bytes --]

On Thu, 17 Oct 2024, Jonathan Cameron wrote:

> On Wed,  9 Oct 2024 12:52:16 +0300
> Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:
> 
> > PCIe Bandwidth Controller performs RMW accesses the Link Control 2
> > Register which can occur concurrently to other sources of Link Control
> > 2 Register writes. Therefore, add Link Control 2 Register among the PCI
> > Express Capability Registers that need RMW locking.
> > 
> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > Reviewed-by: Lukas Wunner <lukas@wunner.de>
> Totally trivial comment inline.
> 
> LGTM
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> > ---
> >  Documentation/PCI/pciebus-howto.rst | 14 +++++++++-----
> >  include/linux/pci.h                 |  1 +
> >  2 files changed, 10 insertions(+), 5 deletions(-)
> > 
> > diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst
> > index f344452651e1..375d9ce171f6 100644
> > --- a/Documentation/PCI/pciebus-howto.rst
> > +++ b/Documentation/PCI/pciebus-howto.rst
> > @@ -217,8 +217,12 @@ capability structure except the PCI Express capability structure,
> >  that is shared between many drivers including the service drivers.
> >  RMW Capability accessors (pcie_capability_clear_and_set_word(),
> >  pcie_capability_set_word(), and pcie_capability_clear_word()) protect
> > -a selected set of PCI Express Capability Registers (Link Control
> > -Register and Root Control Register). Any change to those registers
> > -should be performed using RMW accessors to avoid problems due to
> > -concurrent updates. For the up-to-date list of protected registers,
> > -see pcie_capability_clear_and_set_word().
> > +a selected set of PCI Express Capability Registers:
> > +
> > +* Link Control Register
> > +* Root Control Register
> > +* Link Control 2 Register
> > +
> > +Any change to those registers should be performed using RMW accessors to
> > +avoid problems due to concurrent updates. For the up-to-date list of
> > +protected registers, see pcie_capability_clear_and_set_word().
> 
> If I were super fussy I'd ask for a precursor patch doing the reformat.
> 
> Meh - up to Bjorn, but for me this is small enough to not be worth
> the effort.

Hi Jonathan,

Thanks. Since you brought it up, I've no problem in splitting the 
reformatting into own patch, it won't take more than a minute
anyway to do that change.

-- 
 i.

> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > index 573b4c4c2be6..be5ed534c39c 100644
> > --- a/include/linux/pci.h
> > +++ b/include/linux/pci.h
> > @@ -1274,6 +1274,7 @@ static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
> >  {
> >  	switch (pos) {
> >  	case PCI_EXP_LNKCTL:
> > +	case PCI_EXP_LNKCTL2:
> >  	case PCI_EXP_RTCTL:
> >  		return pcie_capability_clear_and_set_word_locked(dev, pos,
> >  								 clear, set);
> 
> 

  reply	other threads:[~2024-10-17 10:30 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-09  9:52 [PATCH v8 0/8] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 1/8] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-10-17 10:12   ` Jonathan Cameron
2024-10-17 10:30     ` Ilpo Järvinen [this message]
2024-10-09  9:52 ` [PATCH v8 2/8] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-10-17 10:25   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 3/8] PCI: Refactor pcie_update_link_speed() Ilpo Järvinen
2024-10-17 10:26   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 4/8] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-10-17 10:29   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 5/8] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-10-17 10:48   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 6/8] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-10-17 11:02   ` Jonathan Cameron
2024-10-17 13:16     ` Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 7/8] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-10-17 11:04   ` Jonathan Cameron
2024-10-17 12:16     ` Ilpo Järvinen
2024-10-17 12:58       ` Rafael J. Wysocki
2024-10-17 13:02         ` Ilpo Järvinen
2024-10-17 13:28           ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 8/8] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2024-10-17 11:08   ` Jonathan Cameron

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