public inbox for linux-pci@vger.kernel.org
 help / color / mirror / Atom feed
From: "Bowman, Terry" <terry.bowman@amd.com>
To: Alejandro Lucero Palau <alucerop@amd.com>,
	linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
	dave@stgolabs.net, jonathan.cameron@huawei.com,
	dave.jiang@intel.com, alison.schofield@intel.com,
	vishal.l.verma@intel.com, dan.j.williams@intel.com,
	bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com,
	oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com,
	nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
	lukas@wunner.de, PradeepVineshReddy.Kodamati@amd.com,
	Li Ming <ming.li@zohomail.com>
Subject: Re: [PATCH v4 15/15] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports
Date: Fri, 13 Dec 2024 09:22:04 -0600	[thread overview]
Message-ID: <8b5781f0-3eca-452a-b89d-e6c3a8ba924c@amd.com> (raw)
In-Reply-To: <15da313a-b289-fb06-2f1b-eba5dfe5d30c@amd.com>




On 12/12/2024 4:44 AM, Alejandro Lucero Palau wrote:
> On 12/12/24 09:44, Alejandro Lucero Palau wrote:
>> On 12/11/24 23:40, Terry Bowman wrote:
>>> The AER service driver enables PCIe Uncorrectable Internal Errors 
>>> (UIE) and
>>> Correctable Internal errors (CIE) for CXL Root Ports and CXL RCEC's. The
>>> UIE and CIE are used in reporting CXL Protocol Errors. The same UIE/CIE
>>> enablement is needed for CXL PCIe Upstream and Downstream Ports 
>>> inorder to
>>> notify the associated Root Port and OS.[1]
>>>
>>> Export the AER service driver's pci_aer_unmask_internal_errors() 
>>> function
>>> to CXL namespace.
>>>
>>> Remove the function's dependency on the CONFIG_PCIEAER_CXL kernel config
>>> because it is now an exported function.
>>>
>>> Call pci_aer_unmask_internal_errors() during RAS initialization in:
>>> cxl_uport_init_ras_reporting() and cxl_dport_init_ras_reporting().
>>>
>>> [1] PCIe Base Spec r6.2-1.0, 6.2.3.2.2 Masking Individual Errors
>>>
>>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>>> ---
>>>   drivers/cxl/core/pci.c | 2 ++
>>>   drivers/pci/pcie/aer.c | 5 +++--
>>>   include/linux/aer.h    | 1 +
>>>   3 files changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>>> index 9734a4c55b29..740ac5d8809f 100644
>>> --- a/drivers/cxl/core/pci.c
>>> +++ b/drivers/cxl/core/pci.c
>>> @@ -886,6 +886,7 @@ void cxl_uport_init_ras_reporting(struct cxl_port 
>>> *port)
>>>         cxl_assign_port_error_handlers(pdev);
>>>       devm_add_action_or_reset(port->uport_dev, 
>>> cxl_clear_port_error_handlers, pdev);
>>> +    pci_aer_unmask_internal_errors(pdev);
>>>   }
>>>   EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL);
>>>   @@ -920,6 +921,7 @@ void cxl_dport_init_ras_reporting(struct 
>>> cxl_dport *dport)
>>>         cxl_assign_port_error_handlers(pdev);
>>>       devm_add_action_or_reset(dport_dev, 
>>> cxl_clear_port_error_handlers, pdev);
>>> +    pci_aer_unmask_internal_errors(pdev);
>>>   }
>>>   EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL);
>>>   diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
>>> index 861521872318..0fa1b1ed48c9 100644
>>> --- a/drivers/pci/pcie/aer.c
>>> +++ b/drivers/pci/pcie/aer.c
>>> @@ -949,7 +949,6 @@ static bool is_internal_error(struct aer_err_info 
>>> *info)
>>>       return info->status & PCI_ERR_UNC_INTN;
>>>   }
>>>   -#ifdef CONFIG_PCIEAER_CXL
>>
>> This ifdef move puzzles me. I would expect to use it when the next 
>> function is invoked instead of moving it here.
>>
>> It seems weird to have such a config but code using those related 
>> functions not aware of it.
>>
>>
>>>   /**
>>>    * pci_aer_unmask_internal_errors - unmask internal errors
>>>    * @dev: pointer to the pcie_dev data structure
>>> @@ -960,7 +959,7 @@ static bool is_internal_error(struct aer_err_info 
>>> *info)
>>>    * Note: AER must be enabled and supported by the device which must be
>>>    * checked in advance, e.g. with pcie_aer_is_native().
>>>    */
>>> -static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
>>> +void pci_aer_unmask_internal_errors(struct pci_dev *dev)
>>>   {
>>>       int aer = dev->aer_cap;
>>>       u32 mask;
>>> @@ -973,7 +972,9 @@ static void pci_aer_unmask_internal_errors(struct 
>>> pci_dev *dev)
>>>       mask &= ~PCI_ERR_COR_INTERNAL;
>>>       pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
>>>   }
>>> +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, CXL);
>
> Forgot to mention all these exports are changing in 6.13 with the second 
> macro param being now an string, so just
>
> EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL");
>
>
> Not affected in the codebase linked to this patchset, but I hope it 
> helps you when getting weird errors with a newer kernel.

Thanks for the heads-up?

- Terry

>
>>>   +#ifdef CONFIG_PCIEAER_CXL
>>>   static bool is_cxl_mem_dev(struct pci_dev *dev)
>>>   {
>>>       /*
>>> diff --git a/include/linux/aer.h b/include/linux/aer.h
>>> index 4b97f38f3fcf..093293f9f12b 100644
>>> --- a/include/linux/aer.h
>>> +++ b/include/linux/aer.h
>>> @@ -55,5 +55,6 @@ void pci_print_aer(struct pci_dev *dev, int 
>>> aer_severity,
>>>   int cper_severity_to_aer(int cper_severity);
>>>   void aer_recover_queue(int domain, unsigned int bus, unsigned int 
>>> devfn,
>>>                  int severity, struct aer_capability_regs *aer_regs);
>>> +void pci_aer_unmask_internal_errors(struct pci_dev *dev);
>>>   #endif //_AER_H_


  reply	other threads:[~2024-12-13 15:22 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-11 23:39 [PATCH v4 0/15] Enable CXL PCIe Port protocol error handling and logging Terry Bowman
2024-12-11 23:39 ` [PATCH v4 01/15] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2024-12-11 23:39 ` [PATCH v4 02/15] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2024-12-11 23:39 ` [PATCH v4 03/15] cxl/pci: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2024-12-11 23:39 ` [PATCH v4 04/15] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2024-12-12  1:34   ` Li Ming
2024-12-12 19:59     ` Bowman, Terry
2024-12-14 13:34       ` Li Ming
2024-12-11 23:39 ` [PATCH v4 05/15] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2024-12-11 23:39 ` [PATCH v4 06/15] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe Port devices Terry Bowman
2024-12-24 18:28   ` Jonathan Cameron
2024-12-11 23:39 ` [PATCH v4 07/15] PCI/AER: Add CXL PCIe Port Uncorrectable Error recovery in AER service driver Terry Bowman
2024-12-12  9:28   ` Alejandro Lucero Palau
2024-12-13 15:07     ` Bowman, Terry
2024-12-24 18:31   ` Jonathan Cameron
2024-12-11 23:39 ` [PATCH v4 08/15] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2024-12-12 10:36   ` Alejandro Lucero Palau
2024-12-13 15:10     ` Bowman, Terry
2024-12-24 18:38   ` Jonathan Cameron
2024-12-11 23:39 ` [PATCH v4 09/15] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2024-12-24 18:41   ` Jonathan Cameron
2024-12-11 23:39 ` [PATCH v4 10/15] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2024-12-12 10:38   ` Alejandro Lucero Palau
2024-12-24 18:42   ` Jonathan Cameron
2024-12-11 23:39 ` [PATCH v4 11/15] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2024-12-11 23:39 ` [PATCH v4 12/15] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2024-12-12  2:19   ` Li Ming
2024-12-24 18:43   ` Jonathan Cameron
2024-12-11 23:40 ` [PATCH v4 13/15] cxl/pci: Add trace logging " Terry Bowman
2024-12-12  9:46   ` Alejandro Lucero Palau
2024-12-24 18:46   ` Jonathan Cameron
2024-12-26 17:01     ` Bowman, Terry
2024-12-11 23:40 ` [PATCH v4 14/15] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2024-12-12  2:31   ` Li Ming
2024-12-17 14:39     ` Bowman, Terry
2024-12-24 18:50   ` Jonathan Cameron
2024-12-26 17:07     ` Bowman, Terry
2025-01-07 11:32       ` Jonathan Cameron
2024-12-11 23:40 ` [PATCH v4 15/15] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2024-12-12  9:44   ` Alejandro Lucero Palau
2024-12-12 10:44     ` Alejandro Lucero Palau
2024-12-13 15:22       ` Bowman, Terry [this message]
2024-12-13 15:34     ` Bowman, Terry
2024-12-24 18:53   ` Jonathan Cameron
2024-12-26 17:19     ` Bowman, Terry

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=8b5781f0-3eca-452a-b89d-e6c3a8ba924c@amd.com \
    --to=terry.bowman@amd.com \
    --cc=Benjamin.Cheatham@amd.com \
    --cc=PradeepVineshReddy.Kodamati@amd.com \
    --cc=Smita.KoralahalliChannabasappa@amd.com \
    --cc=alison.schofield@intel.com \
    --cc=alucerop@amd.com \
    --cc=bhelgaas@google.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=ira.weiny@intel.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lukas@wunner.de \
    --cc=mahesh@linux.ibm.com \
    --cc=ming.li@zohomail.com \
    --cc=nathan.fontenot@amd.com \
    --cc=nifan.cxl@gmail.com \
    --cc=oohall@gmail.com \
    --cc=rrichter@amd.com \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox