* [PATCH v1] PCI: imx6: Don't remove MSI capability For i.MX7D/i.MX8M
@ 2026-03-13 6:49 Richard Zhu
2026-03-13 7:32 ` Alexander Stein
0 siblings, 1 reply; 3+ messages in thread
From: Richard Zhu @ 2026-03-13 6:49 UTC (permalink / raw)
To: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
shawnguo, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, imx, linux-kernel, Richard Zhu
The MSI trigger mechanism for endpoint devices connected to i.MX7D,
i.MX8MM, and i.MX8MQ PCIe root complex ports depends on the MSI
capability register settings in the root complex. Removing the MSI
capability breaks MSI functionality for these endpoints.
Preserve the MSI capability for i.MX7D/i.MX8M PCIe root complex to
maintain MSI functionality.
Fixes: f5cd8a929c825 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 81a7093494c8..b86d22db4a13 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -41,6 +41,7 @@
#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
+#define IMX8MM_PCIE_MSI_CAP_OFFSET 0x50
#define IMX95_PCIE_PHY_GEN_CTRL 0x0
#define IMX95_PCIE_REF_USE_PAD BIT(17)
@@ -117,6 +118,7 @@ enum imx_pcie_variants {
#define IMX_PCIE_FLAG_HAS_LUT BIT(10)
#define IMX_PCIE_FLAG_8GT_ECN_ERR051586 BIT(11)
#define IMX_PCIE_FLAG_SKIP_L23_READY BIT(12)
+#define IMX_PCIE_FLAG_KEEP_MSI_CAP BIT(13)
#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
@@ -976,10 +978,17 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
{
struct imx_pcie *imx_pcie = to_imx_pcie(pci);
struct device *dev = pci->dev;
- u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ u8 offset;
u32 tmp;
int ret;
+ if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_KEEP_MSI_CAP) {
+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM);
+ dw_pcie_dbi_ro_wr_en(pci);
+ dw_pcie_writeb_dbi(pci, offset + 1, IMX8MM_PCIE_MSI_CAP_OFFSET);
+ dw_pcie_dbi_ro_wr_dis(pci);
+ }
+
if (!(imx_pcie->drvdata->flags &
IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND)) {
imx_pcie_ltssm_enable(dev);
@@ -991,6 +1000,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
* started in Gen2 mode, there is a possibility the devices on the
* bus will not be detected at all. This happens with PCIe switches.
*/
+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
dw_pcie_dbi_ro_wr_en(pci);
tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
tmp &= ~PCI_EXP_LNKCAP_SLS;
@@ -1907,6 +1917,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
[IMX7D] = {
.variant = IMX7D,
.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_KEEP_MSI_CAP |
IMX_PCIE_FLAG_HAS_APP_RESET |
IMX_PCIE_FLAG_SKIP_L23_READY |
IMX_PCIE_FLAG_HAS_PHY_RESET,
@@ -1919,6 +1930,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
[IMX8MQ] = {
.variant = IMX8MQ,
.flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_KEEP_MSI_CAP |
IMX_PCIE_FLAG_HAS_PHY_RESET |
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx8mq-iomuxc-gpr",
@@ -1933,6 +1945,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
[IMX8MM] = {
.variant = IMX8MM,
.flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_KEEP_MSI_CAP |
IMX_PCIE_FLAG_HAS_PHYDRV |
IMX_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mm-iomuxc-gpr",
--
2.37.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v1] PCI: imx6: Don't remove MSI capability For i.MX7D/i.MX8M
2026-03-13 6:49 [PATCH v1] PCI: imx6: Don't remove MSI capability For i.MX7D/i.MX8M Richard Zhu
@ 2026-03-13 7:32 ` Alexander Stein
2026-03-13 7:34 ` Hongxing Zhu
0 siblings, 1 reply; 3+ messages in thread
From: Alexander Stein @ 2026-03-13 7:32 UTC (permalink / raw)
To: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
shawnguo, s.hauer, kernel, festevam, linux-arm-kernel
Cc: linux-pci, linux-arm-kernel, imx, linux-kernel, Richard Zhu,
Richard Zhu
Am Freitag, 13. März 2026, 07:49:27 CET schrieb Richard Zhu:
> The MSI trigger mechanism for endpoint devices connected to i.MX7D,
> i.MX8MM, and i.MX8MQ PCIe root complex ports depends on the MSI
> capability register settings in the root complex. Removing the MSI
> capability breaks MSI functionality for these endpoints.
>
> Preserve the MSI capability for i.MX7D/i.MX8M PCIe root complex to
> maintain MSI functionality.
Does this apply to i.MX8MP as well?
Best regards,
Alexander
>
> Fixes: f5cd8a929c825 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller")
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 81a7093494c8..b86d22db4a13 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -41,6 +41,7 @@
> #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
> #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
> +#define IMX8MM_PCIE_MSI_CAP_OFFSET 0x50
>
> #define IMX95_PCIE_PHY_GEN_CTRL 0x0
> #define IMX95_PCIE_REF_USE_PAD BIT(17)
> @@ -117,6 +118,7 @@ enum imx_pcie_variants {
> #define IMX_PCIE_FLAG_HAS_LUT BIT(10)
> #define IMX_PCIE_FLAG_8GT_ECN_ERR051586 BIT(11)
> #define IMX_PCIE_FLAG_SKIP_L23_READY BIT(12)
> +#define IMX_PCIE_FLAG_KEEP_MSI_CAP BIT(13)
>
> #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
>
> @@ -976,10 +978,17 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
> {
> struct imx_pcie *imx_pcie = to_imx_pcie(pci);
> struct device *dev = pci->dev;
> - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + u8 offset;
> u32 tmp;
> int ret;
>
> + if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_KEEP_MSI_CAP) {
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM);
> + dw_pcie_dbi_ro_wr_en(pci);
> + dw_pcie_writeb_dbi(pci, offset + 1, IMX8MM_PCIE_MSI_CAP_OFFSET);
> + dw_pcie_dbi_ro_wr_dis(pci);
> + }
> +
> if (!(imx_pcie->drvdata->flags &
> IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND)) {
> imx_pcie_ltssm_enable(dev);
> @@ -991,6 +1000,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
> * started in Gen2 mode, there is a possibility the devices on the
> * bus will not be detected at all. This happens with PCIe switches.
> */
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> dw_pcie_dbi_ro_wr_en(pci);
> tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> tmp &= ~PCI_EXP_LNKCAP_SLS;
> @@ -1907,6 +1917,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> [IMX7D] = {
> .variant = IMX7D,
> .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> + IMX_PCIE_FLAG_KEEP_MSI_CAP |
> IMX_PCIE_FLAG_HAS_APP_RESET |
> IMX_PCIE_FLAG_SKIP_L23_READY |
> IMX_PCIE_FLAG_HAS_PHY_RESET,
> @@ -1919,6 +1930,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> [IMX8MQ] = {
> .variant = IMX8MQ,
> .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
> + IMX_PCIE_FLAG_KEEP_MSI_CAP |
> IMX_PCIE_FLAG_HAS_PHY_RESET |
> IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> @@ -1933,6 +1945,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> [IMX8MM] = {
> .variant = IMX8MM,
> .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> + IMX_PCIE_FLAG_KEEP_MSI_CAP |
> IMX_PCIE_FLAG_HAS_PHYDRV |
> IMX_PCIE_FLAG_HAS_APP_RESET,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH v1] PCI: imx6: Don't remove MSI capability For i.MX7D/i.MX8M
2026-03-13 7:32 ` Alexander Stein
@ 2026-03-13 7:34 ` Hongxing Zhu
0 siblings, 0 replies; 3+ messages in thread
From: Hongxing Zhu @ 2026-03-13 7:34 UTC (permalink / raw)
To: Alexander Stein, Frank Li, l.stach@pengutronix.de,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
robh@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
linux-arm-kernel@lists.infradead.org
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, linux-kernel@vger.kernel.org
> -----Original Message-----
> From: Alexander Stein <alexander.stein@ew.tq-group.com>
> Sent: 2026年3月13日 15:33
> To: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; robh@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com;
> linux-arm-kernel@lists.infradead.org
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org; Hongxing Zhu
> <hongxing.zhu@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>
> Subject: Re: [PATCH v1] PCI: imx6: Don't remove MSI capability For
> i.MX7D/i.MX8M
>
> Am Freitag, 13. März 2026, 07:49:27 CET schrieb Richard Zhu:
> > The MSI trigger mechanism for endpoint devices connected to i.MX7D,
> > i.MX8MM, and i.MX8MQ PCIe root complex ports depends on the MSI
> > capability register settings in the root complex. Removing the MSI
> > capability breaks MSI functionality for these endpoints.
> >
> > Preserve the MSI capability for i.MX7D/i.MX8M PCIe root complex to
> > maintain MSI functionality.
>
> Does this apply to i.MX8MP as well?
>
Hi Alex:
i.MX8MP doesn't need this commit refer to my local tests.
Best Regards
Richard Zhu
> Best regards,
> Alexander
>
> >
> > Fixes: f5cd8a929c825 ("PCI: dwc: Remove MSI/MSIX capability for Root
> > Port if iMSI-RX is used as MSI controller")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 15 ++++++++++++++-
> > 1 file changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 81a7093494c8..b86d22db4a13 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -41,6 +41,7 @@
> > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> > #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
> > #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
> > +#define IMX8MM_PCIE_MSI_CAP_OFFSET 0x50
> >
> > #define IMX95_PCIE_PHY_GEN_CTRL 0x0
> > #define IMX95_PCIE_REF_USE_PAD BIT(17)
> > @@ -117,6 +118,7 @@ enum imx_pcie_variants {
> > #define IMX_PCIE_FLAG_HAS_LUT BIT(10)
> > #define IMX_PCIE_FLAG_8GT_ECN_ERR051586 BIT(11)
> > #define IMX_PCIE_FLAG_SKIP_L23_READY BIT(12)
> > +#define IMX_PCIE_FLAG_KEEP_MSI_CAP BIT(13)
> >
> > #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
> >
> > @@ -976,10 +978,17 @@ static int imx_pcie_start_link(struct dw_pcie
> > *pci) {
> > struct imx_pcie *imx_pcie = to_imx_pcie(pci);
> > struct device *dev = pci->dev;
> > - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > + u8 offset;
> > u32 tmp;
> > int ret;
> >
> > + if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_KEEP_MSI_CAP) {
> > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM);
> > + dw_pcie_dbi_ro_wr_en(pci);
> > + dw_pcie_writeb_dbi(pci, offset + 1,
> IMX8MM_PCIE_MSI_CAP_OFFSET);
> > + dw_pcie_dbi_ro_wr_dis(pci);
> > + }
> > +
> > if (!(imx_pcie->drvdata->flags &
> > IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND)) {
> > imx_pcie_ltssm_enable(dev);
> > @@ -991,6 +1000,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
> > * started in Gen2 mode, there is a possibility the devices on the
> > * bus will not be detected at all. This happens with PCIe switches.
> > */
> > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > dw_pcie_dbi_ro_wr_en(pci);
> > tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > tmp &= ~PCI_EXP_LNKCAP_SLS;
> > @@ -1907,6 +1917,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > [IMX7D] = {
> > .variant = IMX7D,
> > .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> > + IMX_PCIE_FLAG_KEEP_MSI_CAP |
> > IMX_PCIE_FLAG_HAS_APP_RESET |
> > IMX_PCIE_FLAG_SKIP_L23_READY |
> > IMX_PCIE_FLAG_HAS_PHY_RESET,
> > @@ -1919,6 +1930,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > [IMX8MQ] = {
> > .variant = IMX8MQ,
> > .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
> > + IMX_PCIE_FLAG_KEEP_MSI_CAP |
> > IMX_PCIE_FLAG_HAS_PHY_RESET |
> > IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> > .gpr = "fsl,imx8mq-iomuxc-gpr",
> > @@ -1933,6 +1945,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > [IMX8MM] = {
> > .variant = IMX8MM,
> > .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> > + IMX_PCIE_FLAG_KEEP_MSI_CAP |
> > IMX_PCIE_FLAG_HAS_PHYDRV |
> > IMX_PCIE_FLAG_HAS_APP_RESET,
> > .gpr = "fsl,imx8mm-iomuxc-gpr",
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-gr/
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>
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2026-03-13 6:49 [PATCH v1] PCI: imx6: Don't remove MSI capability For i.MX7D/i.MX8M Richard Zhu
2026-03-13 7:32 ` Alexander Stein
2026-03-13 7:34 ` Hongxing Zhu
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