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From: Aksh Garg <a-garg7@ti.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
	"mani@kernel.org" <mani@kernel.org>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	"kwilczynski@kernel.org" <kwilczynski@kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"yoshihiro.shimoda.uh@renesas.com"
	<yoshihiro.shimoda.uh@renesas.com>,
	"fancer.lancer@gmail.com" <fancer.lancer@gmail.com>,
	"Zhiqiang.Hou@nxp.com" <Zhiqiang.Hou@nxp.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
	"cassel@kernel.org" <cassel@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Vadapalli, Siddharth" <s-vadapalli@ti.com>,
	"Anwar, Md Danish" <danishanwar@ti.com>
Subject: Re: [PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function
Date: Mon, 9 Mar 2026 10:19:01 +0530	[thread overview]
Message-ID: <95b73073-5a94-4e69-820c-7154be72056a@ti.com> (raw)
In-Reply-To: <20260306184519.GA131984@bhelgaas>



On 07/03/26 00:15, Bjorn Helgaas wrote:
> On Tue, Feb 24, 2026 at 02:08:16PM +0530, Aksh Garg wrote:
>> The MSI-X configuration code reads from the correct physical function's
>> register space using dw_pcie_ep_readw_dbi(), but writes back only to
>> PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
>> MSI-X configuration for other PFs.
>>
>> Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
>> register space, matching the read operation.
> 
> Is this another case of using "PF" in a non-SR-IOV context, as I asked
> about here?
> 
>    https://lore.kernel.org/all/20260223185558.GA3701139@bhelgaas
> 
> I do not want to use "PF" unless we're talking about a device with an
> SR-IOV Capability and we're doing something specific to SR-IOV.

I apologize to commit the same mistake here after your feedback. While
posting this series again, I made changes to patch 2/2, but forgot to
look at the commit message for this patch.

> 
>> Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
>> Reviewed-by: Niklas Cassel <cassel@kernel.org>
>> Signed-off-by: Aksh Garg <a-garg7@ti.com>
>> ---
>>
>> Changes since v1:
>> - None
>>
>> v1: https://lore.kernel.org/all/20260202072758.101845-2-a-garg7@ti.com/
>>
>>   drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
>> index 7e7844ff0f7e..771241e1a2c9 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
>> @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>   	val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
>>   	val &= ~PCI_MSIX_FLAGS_QSIZE;
>>   	val |= nr_irqs - 1; /* encoded as N-1 */
>> -	dw_pcie_writew_dbi(pci, reg, val);
>> +	dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
>>   
>>   	reg = ep_func->msix_cap + PCI_MSIX_TABLE;
>>   	val = offset | bir;
>> -- 
>> 2.34.1
>>


  reply	other threads:[~2026-03-09  4:49 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-24  8:38 [PATCH v3 0/2] PCI: dwc: ep: Multi-function endpoint configuration fixes Aksh Garg
2026-02-24  8:38 ` [PATCH v3 1/2] PCI: dwc: ep: Fix MSI-X configuration to write to correct physical function Aksh Garg
2026-03-06 18:45   ` Bjorn Helgaas
2026-03-09  4:49     ` Aksh Garg [this message]
2026-03-09  6:31     ` Manivannan Sadhasivam
2026-02-24  8:38 ` [PATCH v3 2/2] PCI: dwc: ep: Mirror the max link width and speed fields to all functions Aksh Garg
2026-03-05  5:04 ` [PATCH v3 0/2] PCI: dwc: ep: Multi-function endpoint configuration fixes Manivannan Sadhasivam

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