From: Jon Hunter <jonathanh@nvidia.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: manivannan.sadhasivam@oss.qualcomm.com,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
"David E. Box" <david.e.box@linux.intel.com>,
"Kai-Heng Feng" <kai.heng.feng@canonical.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"Chia-Lin Kao" <acelan.kao@canonical.com>,
"Bjorn Helgaas" <helgaas@kernel.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for devicetree platforms
Date: Thu, 22 Jan 2026 13:43:41 +0000 [thread overview]
Message-ID: <9a76a4a7-c02c-436a-8f69-57606a6b2bed@nvidia.com> (raw)
In-Reply-To: <76sr3yuwdaon3o3u5dfjycwlxhxcarid5tevgtao6aaapvwbzd@e7bam35dzt3k>
On 22/01/2026 13:17, Manivannan Sadhasivam wrote:
...
>> Since this commit was added in Linux v6.18, I have been observing a suspend
>> test failures on some of our boards. The suspend test suspends the devices
>> for 20 secs and before this change the board would resume in about ~27 secs
>> (including the 20 sec sleep). After this change the board would take over 80
>> secs to resume and this triggered a failure.
>>
>> Looking at the logs, I can see it is the NVMe device on the board that is
>> having an issue, and I see the reset failing ...
>>
>> [ 945.754939] r8169 0007:01:00.0 enP7p1s0: Link is Up - 1Gbps/Full -
>> flow control rx/tx
>> [ 1002.467432] nvme nvme0: I/O tag 12 (400c) opcode 0x9 (Admin Cmd) QID
>> 0 timeout, reset controller
>> [ 1002.493713] nvme nvme0: 12/0/0 default/read/poll queues
>> [ 1003.050448] nvme nvme0: ctrl state 1 is not RESETTING
>> [ 1003.050481] OOM killer enabled.
>> [ 1003.054035] nvme nvme0: Disabling device after reset failure: -19
>>
>> From the above timestamps the delay is coming from the NVMe. I see this
>> issue on several boards with different NVMe devices and I can workaround
>> this by disabling ASPM L0/L1 for these devices ...
>>
>> DECLARE_PCI_FIXUP_HEADER(0x15b7, 0x5011, quirk_disable_aspm_l0s_l1);
>> DECLARE_PCI_FIXUP_HEADER(0x15b7, 0x5036, quirk_disable_aspm_l0s_l1);
>> DECLARE_PCI_FIXUP_HEADER(0x1b4b, 0x1322, quirk_disable_aspm_l0s_l1);
>> DECLARE_PCI_FIXUP_HEADER(0xc0a9, 0x540a, quirk_disable_aspm_l0s_l1);
>>
>> I am curious if you have seen any similar issues?
>>
>
> Marek reported a similar issue on ARM Juno board [1] on which one of the switch
> downstream port failed to come up while *entering* system suspend. But I was
> clueless as to why the device fails to function only while entering system
> suspend and not during runtime. I suspect something is going wrong in the
> suspend path.
>
> In your case, looks like the device is failing while resuming from suspend. Did
> you see any error log during suspend as well?
I don't see any errors on entering suspend, just resuming from suspend.
One other thing that I notice, on resuming in a good case I see ...
tegra194-pcie 141e0000.pcie: Link didn't transition to L2 state
In a bad case I see ...
tegra194-pcie 141e0000.pcie: Link didn't transition to L2 state
tegra194-pcie 14160000.pcie: Link didn't transition to L2 state
tegra194-pcie 14160000.pcie: Link didn't go to detect state
It appears that this is related because ...
tegra194-pcie 14160000.pcie: PCI host bridge to bus 0004:00
...
nvme nvme0: pci function 0004:01:00.0
>> Other PCIe devices seem to be OK (like the realtek r8169) but just the NVMe
>> is having issues. So I am trying to figure out the best way to resolve this?
>>
>
> First let's try to isolate the issue to L0s or L1. Can you try disabling L0s
> first, then L1?
Yes I will try this today.
Jon
--
nvpublic
next prev parent reply other threads:[~2026-01-22 13:43 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-22 16:16 [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Manivannan Sadhasivam via B4 Relay
2025-09-22 16:16 ` [PATCH v2 1/2] PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for " Manivannan Sadhasivam via B4 Relay
2025-10-14 16:30 ` FUKAUMI Naoki
2025-10-14 18:49 ` Bjorn Helgaas
2025-10-14 23:33 ` Dragan Simic
2025-10-15 6:22 ` Manivannan Sadhasivam
2025-10-15 11:23 ` Diederik de Haas
2025-10-23 18:57 ` Dragan Simic
2025-10-15 6:26 ` Manivannan Sadhasivam
2025-10-15 7:13 ` FUKAUMI Naoki
2025-10-15 7:50 ` Manivannan Sadhasivam
2025-10-15 9:11 ` Shawn Lin
2025-10-15 9:43 ` Manivannan Sadhasivam
2025-10-15 9:46 ` Niklas Cassel
2025-10-15 10:33 ` Manivannan Sadhasivam
2025-10-15 12:17 ` Niklas Cassel
2025-10-15 13:00 ` Shawn Lin
2025-10-15 15:23 ` Niklas Cassel
2025-10-15 23:30 ` Bjorn Helgaas
2025-10-16 6:46 ` Hongxing Zhu
2025-10-17 3:36 ` Manivannan Sadhasivam
2025-10-17 9:47 ` Shawn Lin
2025-10-17 10:04 ` Manivannan Sadhasivam
2025-10-17 12:19 ` Shawn Lin
2025-10-17 12:54 ` Manivannan Sadhasivam
2025-10-17 13:45 ` Bjorn Helgaas
2025-10-31 6:21 ` Manivannan Sadhasivam
2025-10-15 12:26 ` Diederik de Haas
2025-10-15 22:50 ` Bjorn Helgaas
2025-10-16 17:38 ` Diederik de Haas
2025-10-30 22:14 ` Bjorn Helgaas
2025-10-30 22:16 ` Bjorn Helgaas
2026-01-22 12:12 ` Jon Hunter
2026-01-22 13:17 ` Manivannan Sadhasivam
2026-01-22 13:43 ` Jon Hunter [this message]
2026-01-22 14:39 ` Manivannan Sadhasivam
2026-01-22 15:29 ` Bjorn Helgaas
2026-01-22 17:01 ` Manivannan Sadhasivam
2026-01-22 19:14 ` Jon Hunter
2026-01-23 10:55 ` Jon Hunter
2026-01-23 13:56 ` Manivannan Sadhasivam
2026-01-23 14:39 ` Jon Hunter
2026-02-16 14:03 ` Jon Hunter
2026-02-16 14:18 ` Manivannan Sadhasivam
2026-02-16 14:35 ` Jon Hunter
2026-02-19 17:42 ` Jon Hunter
2026-02-26 10:34 ` Jon Hunter
2026-02-26 11:08 ` Manivannan Sadhasivam
2026-02-26 16:55 ` Jon Hunter
2026-03-03 16:27 ` Manivannan Sadhasivam
2026-02-26 11:16 ` Manivannan Sadhasivam
2026-02-26 16:52 ` Jon Hunter
2026-03-03 16:17 ` Manivannan Sadhasivam
2026-03-06 16:03 ` Jon Hunter
2026-03-09 8:00 ` Manivannan Sadhasivam
2026-02-16 17:19 ` Claudiu Beznea
2026-02-18 13:56 ` Manivannan Sadhasivam
2026-05-07 10:25 ` Jon Hunter
2026-05-11 5:18 ` Manivannan Sadhasivam
2026-05-12 9:07 ` Jon Hunter
2025-09-22 16:16 ` [PATCH v2 2/2] PCI: qcom: Remove the custom ASPM enablement code Manivannan Sadhasivam via B4 Relay
2025-09-23 23:14 ` [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Bjorn Helgaas
2025-11-08 16:18 ` Dmitry Baryshkov
2025-11-11 6:51 ` Val Packett
2025-11-11 7:19 ` Manivannan Sadhasivam
2025-11-11 7:40 ` Val Packett
2025-11-11 10:06 ` Manivannan Sadhasivam
2025-11-11 17:29 ` Val Packett
2025-11-13 4:30 ` Val Packett
2025-11-11 23:33 ` Bjorn Helgaas
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