Re: [PATCH v12 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574

[Varadarajan Narayanan <quic_varada@quicinc.com>]

On Wed, Mar 12, 2025 at 09:46:41AM +0100, Krzysztof Kozlowski wrote:
> On 12/03/2025 09:43, Varadarajan Narayanan wrote:
> > Append the MHI register range to IPQ9574.
>
> Why?

This is needed for ipq5332 to use ipq9574 as fallback compatible.

> > Fixes: e0662dae178d ("dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller")
>
> What is being fixed here?

Ok, will remove this.

> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > New patch introduced in this patchset. MHI range was missed in the
> > initial post
> > ---
> >  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index 8f628939209e..77e66ab8764f 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -175,7 +175,7 @@ allOf:
> >        properties:
> >          reg:
> >            minItems: 5
> > -          maxItems: 5
> > +          maxItems: 6
>
> Why qcom,pcie-ipq6018 gets mhi? Nothing in commit msg mentions ipq6018.

Didn't mention ipq6018 as I was under the impression that 'minItems: 5' would
apply for ipq6018.

> >          reg-names:
> >            items:
> >              - const: dbi # DesignWare PCIe registers
> > @@ -183,6 +183,7 @@ allOf:
> >              - const: atu # ATU address space
> >              - const: parf # Qualcomm specific registers
> >              - const: config # PCIe configuration space
> > +            - const: mhi # MHI registers
>
> Never tested - you introduce new warnings. AGAIN.
>
> Properties xxx and xxx-names must have always the same constraints.

Ok, will add 'minItems: 5' here.

Thanks
Varada