From: Bjorn Helgaas <helgaas@kernel.org>
To: Ben Dooks <ben.dooks@sifive.com>
Cc: Ben Dooks <ben.dooks@codethink.co.uk>,
linux-pci@vger.kernel.org, bhelgaas@google.com,
Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>,
Jude Onyenegecha <jude.onyenegecha@codethink.co.uk>,
Greentime Hu <greentime.hu@sifive.com>,
Jeegar Lakhani <jeegar.lakhani@sifive.com>
Subject: Re: [PATCHv2] pci: add PCI_EXT_CAP_ID_PL_32GT define
Date: Fri, 2 Jun 2023 09:02:08 -0500 [thread overview]
Message-ID: <ZHn2YLESaafG91Uh@bhelgaas> (raw)
In-Reply-To: <b289fea8-e4c8-0fda-d637-daf5e85c66f6@sifive.com>
On Fri, Jun 02, 2023 at 02:08:45PM +0100, Ben Dooks wrote:
> On 31/05/2023 22:37, Bjorn Helgaas wrote:
> > On Wed, May 31, 2023 at 10:57:13AM +0100, Ben Dooks wrote:
> > > From: Ben Dooks <ben.dooks@sifive.com>
> > >
> > > Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that
> > > will want this whilst doing Gen5/Gen6 accesses.
> > >
> > > Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> > > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> >
> > I applied this to pci/enumeration for v6.5, thanks.
> >
> > But I'm very curious about where you expect this to be used.
>
> We have an upcoming driver that has gen5 phy and config requirements.
I guess a better question would have been whether
PCI_EXT_CAP_ID_PL_32GT is best used in individual drivers or in the
PCI core. Since it's in the PCIe base spec and doesn't look like it
should be device-specific, it might be a candidate for supporting in
the PCI core somehow so it doesn't get reimplemented in several
places.
Bjorn
prev parent reply other threads:[~2023-06-02 14:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 9:57 [PATCHv2] pci: add PCI_EXT_CAP_ID_PL_32GT define Ben Dooks
2023-05-31 21:37 ` Bjorn Helgaas
2023-06-02 13:08 ` Ben Dooks
2023-06-02 14:02 ` Bjorn Helgaas [this message]
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