From: Ben Dooks <ben.dooks@sifive.com>
To: Bjorn Helgaas <helgaas@kernel.org>,
Ben Dooks <ben.dooks@codethink.co.uk>
Cc: linux-pci@vger.kernel.org, bhelgaas@google.com,
Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>,
Jude Onyenegecha <jude.onyenegecha@codethink.co.uk>,
Greentime Hu <greentime.hu@sifive.com>,
Jeegar Lakhani <jeegar.lakhani@sifive.com>
Subject: Re: [PATCHv2] pci: add PCI_EXT_CAP_ID_PL_32GT define
Date: Fri, 2 Jun 2023 14:08:45 +0100 [thread overview]
Message-ID: <b289fea8-e4c8-0fda-d637-daf5e85c66f6@sifive.com> (raw)
In-Reply-To: <ZHe+E7+GOgnP2fmM@bhelgaas>
On 31/05/2023 22:37, Bjorn Helgaas wrote:
> On Wed, May 31, 2023 at 10:57:13AM +0100, Ben Dooks wrote:
>> From: Ben Dooks <ben.dooks@sifive.com>
>>
>> Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that
>> will want this whilst doing Gen5/Gen6 accesses.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>
> I applied this to pci/enumeration for v6.5, thanks.
>
> But I'm very curious about where you expect this to be used.
We have an upcoming driver that has gen5 phy and config requirements.
next prev parent reply other threads:[~2023-06-02 13:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 9:57 [PATCHv2] pci: add PCI_EXT_CAP_ID_PL_32GT define Ben Dooks
2023-05-31 21:37 ` Bjorn Helgaas
2023-06-02 13:08 ` Ben Dooks [this message]
2023-06-02 14:02 ` Bjorn Helgaas
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