From: Niklas Cassel <cassel@kernel.org>
To: Frank Li <Frank.li@nxp.com>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Damien Le Moal" <dlemoal@kernel.org>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH 2/2] PCI: dwc: ep: Use align addr function for dw_pcie_ep_raise_{msi,msix}_irq()
Date: Thu, 17 Oct 2024 20:54:01 +0200 [thread overview]
Message-ID: <ZxFdSSqbefIiZLN-@ryzen.lan> (raw)
In-Reply-To: <ZxEvFT4+X35/NxWn@lizhi-Precision-Tower-5810>
Hello Frank,
On Thu, Oct 17, 2024 at 11:36:53AM -0400, Frank Li wrote:
> On Thu, Oct 17, 2024 at 03:20:55PM +0200, Niklas Cassel wrote:
> > Use the dw_pcie_ep_align_addr() function to calculate the alignment in
> > dw_pcie_ep_raise_{msi,msix}_irq() instead of open coding the same.
> >
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 18 +++++++++---------
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 20f67fd85e83..9bafa62bed1d 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -503,7 +503,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> > u32 msg_addr_lower, msg_addr_upper, reg;
> > struct dw_pcie_ep_func *ep_func;
> > struct pci_epc *epc = ep->epc;
> > - unsigned int aligned_offset;
> > + size_t msi_mem_size = epc->mem->window.page_size;
> > + size_t offset;
> > u16 msg_ctrl, msg_data;
> > bool has_upper;
> > u64 msg_addr;
> > @@ -531,14 +532,13 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> > }
> > msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
> >
> > - aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> > - msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
> > + msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &msi_mem_size, &offset);
> > ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> > - epc->mem->window.page_size);
> > + msi_mem_size);
> > if (ret)
> > return ret;
> >
> > - writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset);
> > + writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);
> >
> > dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
> >
> > @@ -589,8 +589,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct pci_epf_msix_tbl *msix_tbl;
> > struct dw_pcie_ep_func *ep_func;
> > struct pci_epc *epc = ep->epc;
> > + size_t msi_mem_size = epc->mem->window.page_size;
> > + size_t offset;
> > u32 reg, msg_data, vec_ctrl;
> > - unsigned int aligned_offset;
>
> why not direct use 'aligned_offset' ? just change to size_t.
Because I think that that name was really bad.
aligned_offset sounds like the offset is aligned, but that is not the case.
Now when we have a dw_pcie_ep_align_addr() function, I think that simply
calling the variable offset is less ambiguous. Anyone who isn't sure what
the offset represents can simply read the documentation for the .align_addr
endpoint controller operation.
Kind regards,
Niklas
next prev parent reply other threads:[~2024-10-17 18:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 13:20 [PATCH 0/2] PCI: dwc: ep: Minor alignment cleanups Niklas Cassel
2024-10-17 13:20 ` [PATCH 1/2] PCI: dwc: ep: Fix dw_pcie_ep_align_addr() Niklas Cassel
2024-10-17 15:33 ` Frank Li
2024-11-01 7:12 ` Manivannan Sadhasivam
2024-11-02 11:37 ` Krzysztof Wilczyński
2024-10-17 13:20 ` [PATCH 2/2] PCI: dwc: ep: Use align addr function for dw_pcie_ep_raise_{msi,msix}_irq() Niklas Cassel
2024-10-17 15:36 ` Frank Li
2024-10-17 18:54 ` Niklas Cassel [this message]
2024-10-17 19:36 ` Frank Li
2024-10-31 20:28 ` Bjorn Helgaas
2024-10-31 22:36 ` Damien Le Moal
2024-11-01 18:25 ` Niklas Cassel
2024-11-01 7:16 ` Manivannan Sadhasivam
2024-11-02 11:41 ` Krzysztof Wilczyński
2024-10-20 0:59 ` [PATCH 0/2] PCI: dwc: ep: Minor alignment cleanups Damien Le Moal
2024-10-29 10:25 ` Niklas Cassel
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