* [PATCH 0/3] Standardize link status check to return bool
@ 2025-04-28 17:10 Hans Zhang
2025-04-28 17:10 ` [PATCH 1/3] PCI: dwc: " Hans Zhang
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Hans Zhang @ 2025-04-28 17:10 UTC (permalink / raw)
To: lpieralisi, kw, bhelgaas, jingoohan1, manivannan.sadhasivam
Cc: cassel, robh, linux-pci, linux-kernel, Hans Zhang
1. PCI: dwc: Standardize link status check to return bool.
2. PCI: mobiveil: Refactor link status check.
3. PCI: cadence: Simplify j721e link status check.
Hans Zhang (3):
PCI: dwc: Standardize link status check to return bool.
PCI: mobiveil: Refactor link status check.
PCI: cadence: Simplify j721e link status check.
drivers/pci/controller/cadence/pci-j721e.c | 6 +-----
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-exynos.c | 4 ++--
drivers/pci/controller/dwc/pci-keystone.c | 5 ++---
drivers/pci/controller/dwc/pci-meson.c | 6 +++---
drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.c | 2 +-
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +-
drivers/pci/controller/dwc/pcie-histb.c | 9 +++------
drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
drivers/pci/controller/dwc/pcie-kirin.c | 7 ++-----
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++--
drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +-
drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++-----
drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
drivers/pci/controller/dwc/pcie-uniphier.c | 2 +-
drivers/pci/controller/dwc/pcie-visconti.c | 2 +-
drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 9 ++-------
drivers/pci/controller/mobiveil/pcie-mobiveil.h | 2 +-
21 files changed, 34 insertions(+), 53 deletions(-)
base-commit: 286ed198b899739862456f451eda884558526a9d
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/3] PCI: dwc: Standardize link status check to return bool 2025-04-28 17:10 [PATCH 0/3] Standardize link status check to return bool Hans Zhang @ 2025-04-28 17:10 ` Hans Zhang 2025-04-29 8:05 ` Niklas Cassel 2025-04-28 17:10 ` [PATCH 2/3] PCI: mobiveil: Refactor link status check Hans Zhang ` (2 subsequent siblings) 3 siblings, 1 reply; 8+ messages in thread From: Hans Zhang @ 2025-04-28 17:10 UTC (permalink / raw) To: lpieralisi, kw, bhelgaas, jingoohan1, manivannan.sadhasivam Cc: cassel, robh, linux-pci, linux-kernel, Hans Zhang Modify link_up functions across multiple DWC PCIe controllers to return bool instead of int. Simplify conditional checks by directly returning logical evaluations. This improves code clarity and aligns with PCIe status semantics. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- drivers/pci/controller/dwc/pci-meson.c | 6 +++--- drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++--- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- drivers/pci/controller/dwc/pcie-histb.c | 9 +++------ drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-kirin.c | 7 ++----- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- drivers/pci/controller/dwc/pcie-qcom.c | 2 +- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++----- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- drivers/pci/controller/dwc/pcie-uniphier.c | 2 +- drivers/pci/controller/dwc/pcie-visconti.c | 2 +- 18 files changed, 30 insertions(+), 40 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 33d6bf460ffe..4ef25d14312b 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -118,7 +118,7 @@ static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; } -static int dra7xx_pcie_link_up(struct dw_pcie *pci) +static bool dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index ace736b025b1..d4a25d376b11 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -209,12 +209,12 @@ static struct pci_ops exynos_pci_ops = { .write = exynos_pcie_wr_own_conf, }; -static int exynos_pcie_link_up(struct dw_pcie *pci) +static bool exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep = to_exynos_pcie(pci); u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); - return (val & PCIE_ELBI_XMLH_LINKUP); + return !!(val & PCIE_ELBI_XMLH_LINKUP); } static int exynos_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 76a37368ae4f..968464530e3d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -492,13 +492,12 @@ static struct pci_ops ks_pcie_ops = { * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host * controller driver information. */ -static int ks_pcie_link_up(struct dw_pcie *pci) +static bool ks_pcie_link_up(struct dw_pcie *pci) { u32 val; val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); - val &= PORT_LOGIC_LTSSM_STATE_MASK; - return (val == PORT_LOGIC_LTSSM_STATE_L0); + return (val & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L0; } static void ks_pcie_stop_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index db9482a113e9..787469d1b396 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -335,7 +335,7 @@ static struct pci_ops meson_pci_ops = { .write = pci_generic_config_write, }; -static int meson_pcie_link_up(struct dw_pcie *pci) +static bool meson_pcie_link_up(struct dw_pcie *pci) { struct meson_pcie *mp = to_meson_pcie(pci); struct device *dev = pci->dev; @@ -363,7 +363,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci) dev_dbg(dev, "speed_okay\n"); if (smlh_up && rdlh_up && ltssm_up && speed_okay) - return 1; + return true; cnt++; @@ -371,7 +371,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci) } while (cnt < WAIT_LINKUP_TIMEOUT); dev_err(dev, "error: wait linkup timeout\n"); - return 0; + return false; } static int meson_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index b5c599ccaacf..c2650fd0d458 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -139,7 +139,7 @@ static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie) return ret; } -static int armada8k_pcie_link_up(struct dw_pcie *pci) +static bool armada8k_pcie_link_up(struct dw_pcie *pci) { u32 reg; u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; @@ -147,10 +147,10 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); if ((reg & mask) == mask) - return 1; + return true; dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); - return 0; + return false; } static int armada8k_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 97d76d3dc066..b3615d125942 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -711,7 +711,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) } EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); -int dw_pcie_link_up(struct dw_pcie *pci) +bool dw_pcie_link_up(struct dw_pcie *pci) { u32 val; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 56aafdbcdaca..4dd16aa4b39e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -462,7 +462,7 @@ struct dw_pcie_ops { size_t size, u32 val); void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); - int (*link_up)(struct dw_pcie *pcie); + bool (*link_up)(struct dw_pcie *pcie); enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); @@ -537,7 +537,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val); u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); -int dw_pcie_link_up(struct dw_pcie *pci); +bool dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3c6ab71c996e..ae171a545df6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -183,7 +183,7 @@ static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) PCIE_CLIENT_GENERAL_CON); } -static int rockchip_pcie_link_up(struct dw_pcie *pci) +static bool rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); u32 val = rockchip_pcie_get_ltssm(rockchip); diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index 1f2f4c28a949..a52071589377 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -151,7 +151,7 @@ static struct pci_ops histb_pci_ops = { .write = histb_pcie_wr_own_conf, }; -static int histb_pcie_link_up(struct dw_pcie *pci) +static bool histb_pcie_link_up(struct dw_pcie *pci) { struct histb_pcie *hipcie = to_histb_pcie(pci); u32 regval; @@ -160,11 +160,8 @@ static int histb_pcie_link_up(struct dw_pcie *pci) regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0); status = histb_pcie_readl(hipcie, PCIE_SYS_STAT4); status &= PCIE_LTSSM_STATE_MASK; - if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) && - (status == PCIE_LTSSM_STATE_ACTIVE)) - return 1; - - return 0; + return ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) && + (status == PCIE_LTSSM_STATE_ACTIVE)); } static int histb_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index 278205db60a2..67dd3337b447 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -101,7 +101,7 @@ static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); } -static int keembay_pcie_link_up(struct dw_pcie *pci) +static bool keembay_pcie_link_up(struct dw_pcie *pci) { struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); u32 val; diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index d0e6a3811b00..91559c8b1866 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -586,16 +586,13 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); } -static int kirin_pcie_link_up(struct dw_pcie *pci) +static bool kirin_pcie_link_up(struct dw_pcie *pci) { struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); u32 val; regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val); - if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE) - return 1; - - return 0; + return (val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE; } static int kirin_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 46b1c6d19974..bd37291ba14b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -261,14 +261,14 @@ static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) } } -static int qcom_pcie_dw_link_up(struct dw_pcie *pci) +static bool qcom_pcie_dw_link_up(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); u32 reg; reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS); - return reg & XMLH_LINK_UP; + return !!(reg & XMLH_LINK_UP); } static int qcom_pcie_dw_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index dc98ae63362d..23da0ee48dda 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1221,7 +1221,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) return 0; } -static int qcom_pcie_link_up(struct dw_pcie *pci) +static bool qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index fc872dd35029..ccb94f4a215f 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -87,7 +87,7 @@ struct rcar_gen4_pcie { #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw) /* Common */ -static int rcar_gen4_pcie_link_up(struct dw_pcie *dw) +static bool rcar_gen4_pcie_link_up(struct dw_pcie *dw) { struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); u32 val, mask; diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index ff986ced56b2..8b741b45bebe 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -110,15 +110,12 @@ static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pc MSI_CTRL_INT, &app_reg->int_mask); } -static int spear13xx_pcie_link_up(struct dw_pcie *pci) +static bool spear13xx_pcie_link_up(struct dw_pcie *pci) { struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base; - if (readl(&app_reg->app_status_1) & XMLH_LINK_UP) - return 1; - - return 0; + return !!(readl(&app_reg->app_status_1) & XMLH_LINK_UP); } static int spear13xx_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 5103995cd6c7..304145884b3c 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1027,7 +1027,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) return 0; } -static int tegra_pcie_dw_link_up(struct dw_pcie *pci) +static bool tegra_pcie_dw_link_up(struct dw_pcie *pci) { struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 5757ca3803c9..9d05b3a0579e 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -135,7 +135,7 @@ static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie) return 0; } -static int uniphier_pcie_link_up(struct dw_pcie *pci) +static bool uniphier_pcie_link_up(struct dw_pcie *pci) { struct uniphier_pcie *pcie = to_uniphier_pcie(pci); u32 val, mask; diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c index 318c278e65c8..91f30dc02412 100644 --- a/drivers/pci/controller/dwc/pcie-visconti.c +++ b/drivers/pci/controller/dwc/pcie-visconti.c @@ -121,7 +121,7 @@ static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg) return readl_relaxed(pcie->mpu_base + reg); } -static int visconti_pcie_link_up(struct dw_pcie *pci) +static bool visconti_pcie_link_up(struct dw_pcie *pci) { struct visconti_pcie *pcie = dev_get_drvdata(pci->dev); void __iomem *addr = pcie->ulreg_base; -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] PCI: dwc: Standardize link status check to return bool 2025-04-28 17:10 ` [PATCH 1/3] PCI: dwc: " Hans Zhang @ 2025-04-29 8:05 ` Niklas Cassel 2025-04-29 8:21 ` Hans Zhang 0 siblings, 1 reply; 8+ messages in thread From: Niklas Cassel @ 2025-04-29 8:05 UTC (permalink / raw) To: Hans Zhang Cc: lpieralisi, kw, bhelgaas, jingoohan1, manivannan.sadhasivam, robh, linux-pci, linux-kernel Hello Hans, On Tue, Apr 29, 2025 at 01:10:25AM +0800, Hans Zhang wrote: > Modify link_up functions across multiple DWC PCIe controllers to return > bool instead of int. Simplify conditional checks by directly returning > logical evaluations. This improves code clarity and aligns with PCIe > status semantics. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- > drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- > drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- > drivers/pci/controller/dwc/pci-meson.c | 6 +++--- > drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++--- > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- > drivers/pci/controller/dwc/pcie-histb.c | 9 +++------ > drivers/pci/controller/dwc/pcie-keembay.c | 2 +- > drivers/pci/controller/dwc/pcie-kirin.c | 7 ++----- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- > drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++----- > drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- > drivers/pci/controller/dwc/pcie-uniphier.c | 2 +- > drivers/pci/controller/dwc/pcie-visconti.c | 2 +- > 18 files changed, 30 insertions(+), 40 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c > index 33d6bf460ffe..4ef25d14312b 100644 > --- a/drivers/pci/controller/dwc/pci-dra7xx.c > +++ b/drivers/pci/controller/dwc/pci-dra7xx.c > @@ -118,7 +118,7 @@ static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) > return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; > } > > -static int dra7xx_pcie_link_up(struct dw_pcie *pci) > +static bool dra7xx_pcie_link_up(struct dw_pcie *pci) > { > struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); > u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); > diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c > index ace736b025b1..d4a25d376b11 100644 > --- a/drivers/pci/controller/dwc/pci-exynos.c > +++ b/drivers/pci/controller/dwc/pci-exynos.c > @@ -209,12 +209,12 @@ static struct pci_ops exynos_pci_ops = { > .write = exynos_pcie_wr_own_conf, > }; > > -static int exynos_pcie_link_up(struct dw_pcie *pci) > +static bool exynos_pcie_link_up(struct dw_pcie *pci) > { > struct exynos_pcie *ep = to_exynos_pcie(pci); > u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); > > - return (val & PCIE_ELBI_XMLH_LINKUP); > + return !!(val & PCIE_ELBI_XMLH_LINKUP); !! is not needed here, or in other places. When assigning to the bool any non-zero value becomes 1. !! is usually only needed when needing to store an explicit 1 or 0 in an int. Kind regards, Niklas ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] PCI: dwc: Standardize link status check to return bool 2025-04-29 8:05 ` Niklas Cassel @ 2025-04-29 8:21 ` Hans Zhang 0 siblings, 0 replies; 8+ messages in thread From: Hans Zhang @ 2025-04-29 8:21 UTC (permalink / raw) To: Niklas Cassel Cc: lpieralisi, kw, bhelgaas, jingoohan1, manivannan.sadhasivam, robh, linux-pci, linux-kernel On 2025/4/29 16:05, Niklas Cassel wrote: > Hello Hans, > > On Tue, Apr 29, 2025 at 01:10:25AM +0800, Hans Zhang wrote: >> Modify link_up functions across multiple DWC PCIe controllers to return >> bool instead of int. Simplify conditional checks by directly returning >> logical evaluations. This improves code clarity and aligns with PCIe >> status semantics. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- >> drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- >> drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- >> drivers/pci/controller/dwc/pci-meson.c | 6 +++--- >> drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++--- >> drivers/pci/controller/dwc/pcie-designware.c | 2 +- >> drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- >> drivers/pci/controller/dwc/pcie-histb.c | 9 +++------ >> drivers/pci/controller/dwc/pcie-keembay.c | 2 +- >> drivers/pci/controller/dwc/pcie-kirin.c | 7 ++----- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- >> drivers/pci/controller/dwc/pcie-qcom.c | 2 +- >> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- >> drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++----- >> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- >> drivers/pci/controller/dwc/pcie-uniphier.c | 2 +- >> drivers/pci/controller/dwc/pcie-visconti.c | 2 +- >> 18 files changed, 30 insertions(+), 40 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c >> index 33d6bf460ffe..4ef25d14312b 100644 >> --- a/drivers/pci/controller/dwc/pci-dra7xx.c >> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c >> @@ -118,7 +118,7 @@ static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) >> return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; >> } >> >> -static int dra7xx_pcie_link_up(struct dw_pcie *pci) >> +static bool dra7xx_pcie_link_up(struct dw_pcie *pci) >> { >> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); >> u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); >> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c >> index ace736b025b1..d4a25d376b11 100644 >> --- a/drivers/pci/controller/dwc/pci-exynos.c >> +++ b/drivers/pci/controller/dwc/pci-exynos.c >> @@ -209,12 +209,12 @@ static struct pci_ops exynos_pci_ops = { >> .write = exynos_pcie_wr_own_conf, >> }; >> >> -static int exynos_pcie_link_up(struct dw_pcie *pci) >> +static bool exynos_pcie_link_up(struct dw_pcie *pci) >> { >> struct exynos_pcie *ep = to_exynos_pcie(pci); >> u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); >> >> - return (val & PCIE_ELBI_XMLH_LINKUP); >> + return !!(val & PCIE_ELBI_XMLH_LINKUP); > > !! is not needed here, or in other places. > > When assigning to the bool any non-zero value becomes 1. > > !! is usually only needed when needing to store an explicit 1 or 0 in an int. > Dear Niklas, Thank you very much for your reply and reminder. The next version will be modified. Best regards, Hans ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] PCI: mobiveil: Refactor link status check 2025-04-28 17:10 [PATCH 0/3] Standardize link status check to return bool Hans Zhang 2025-04-28 17:10 ` [PATCH 1/3] PCI: dwc: " Hans Zhang @ 2025-04-28 17:10 ` Hans Zhang 2025-04-28 17:10 ` [PATCH 3/3] PCI: cadence: Simplify j721e " Hans Zhang 2025-05-02 15:36 ` [PATCH 0/3] Standardize link status check to return bool Manivannan Sadhasivam 3 siblings, 0 replies; 8+ messages in thread From: Hans Zhang @ 2025-04-28 17:10 UTC (permalink / raw) To: lpieralisi, kw, bhelgaas, jingoohan1, manivannan.sadhasivam Cc: cassel, robh, linux-pci, linux-kernel, Hans Zhang Update ls_g4_pcie_link_up() to return bool and simplify the LTSSM state check. Align function signature in pcie-mobiveil.h to match the change, ensuring consistency across the Mobiveil PCIe driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 9 ++------- drivers/pci/controller/mobiveil/pcie-mobiveil.h | 2 +- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c index 5af22bee913b..1cf014051296 100644 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c @@ -53,18 +53,13 @@ static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); } -static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci) +static bool ls_g4_pcie_link_up(struct mobiveil_pcie *pci) { struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); u32 state; state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); - state = state & PF_DBG_LTSSM_MASK; - - if (state == PF_DBG_LTSSM_L0) - return 1; - - return 0; + return (state & PF_DBG_LTSSM_MASK) == PF_DBG_LTSSM_L0; } static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index e63abb887ee3..662f17f9bf65 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -160,7 +160,7 @@ struct mobiveil_root_port { }; struct mobiveil_pab_ops { - int (*link_up)(struct mobiveil_pcie *pcie); + bool (*link_up)(struct mobiveil_pcie *pcie); }; struct mobiveil_pcie { -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] PCI: cadence: Simplify j721e link status check 2025-04-28 17:10 [PATCH 0/3] Standardize link status check to return bool Hans Zhang 2025-04-28 17:10 ` [PATCH 1/3] PCI: dwc: " Hans Zhang 2025-04-28 17:10 ` [PATCH 2/3] PCI: mobiveil: Refactor link status check Hans Zhang @ 2025-04-28 17:10 ` Hans Zhang 2025-05-02 15:36 ` [PATCH 0/3] Standardize link status check to return bool Manivannan Sadhasivam 3 siblings, 0 replies; 8+ messages in thread From: Hans Zhang @ 2025-04-28 17:10 UTC (permalink / raw) To: lpieralisi, kw, bhelgaas, jingoohan1, manivannan.sadhasivam Cc: cassel, robh, linux-pci, linux-kernel, Hans Zhang Replace explicit if-else condition with direct return statement in j721e_pcie_link_up(). This reduces code verbosity while maintaining the same logic for detecting PCIe link completion. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/cadence/pci-j721e.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index ef1cfdae33bb..bea1944a7eb2 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -153,11 +153,7 @@ static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) u32 reg; reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); - reg &= LINK_STATUS; - if (reg == LINK_UP_DL_COMPLETED) - return true; - - return false; + return (reg & LINK_STATUS) == LINK_UP_DL_COMPLETED; } static const struct cdns_pcie_ops j721e_pcie_ops = { -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] Standardize link status check to return bool 2025-04-28 17:10 [PATCH 0/3] Standardize link status check to return bool Hans Zhang ` (2 preceding siblings ...) 2025-04-28 17:10 ` [PATCH 3/3] PCI: cadence: Simplify j721e " Hans Zhang @ 2025-05-02 15:36 ` Manivannan Sadhasivam 2025-05-02 16:10 ` Hans Zhang 3 siblings, 1 reply; 8+ messages in thread From: Manivannan Sadhasivam @ 2025-05-02 15:36 UTC (permalink / raw) To: Hans Zhang Cc: lpieralisi, kw, bhelgaas, jingoohan1, cassel, robh, linux-pci, linux-kernel On Tue, Apr 29, 2025 at 01:10:24AM +0800, Hans Zhang wrote: > 1. PCI: dwc: Standardize link status check to return bool. > 2. PCI: mobiveil: Refactor link status check. > 3. PCI: cadence: Simplify j721e link status check. > Thanks for the cleanup. Looks good to me except the redundancy conversion that Niklas noted. So with that change, Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > Hans Zhang (3): > PCI: dwc: Standardize link status check to return bool. > PCI: mobiveil: Refactor link status check. > PCI: cadence: Simplify j721e link status check. > > drivers/pci/controller/cadence/pci-j721e.c | 6 +----- > drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- > drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- > drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- > drivers/pci/controller/dwc/pci-meson.c | 6 +++--- > drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++--- > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- > drivers/pci/controller/dwc/pcie-histb.c | 9 +++------ > drivers/pci/controller/dwc/pcie-keembay.c | 2 +- > drivers/pci/controller/dwc/pcie-kirin.c | 7 ++----- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- > drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++----- > drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- > drivers/pci/controller/dwc/pcie-uniphier.c | 2 +- > drivers/pci/controller/dwc/pcie-visconti.c | 2 +- > drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 9 ++------- > drivers/pci/controller/mobiveil/pcie-mobiveil.h | 2 +- > 21 files changed, 34 insertions(+), 53 deletions(-) > > > base-commit: 286ed198b899739862456f451eda884558526a9d > -- > 2.25.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] Standardize link status check to return bool 2025-05-02 15:36 ` [PATCH 0/3] Standardize link status check to return bool Manivannan Sadhasivam @ 2025-05-02 16:10 ` Hans Zhang 0 siblings, 0 replies; 8+ messages in thread From: Hans Zhang @ 2025-05-02 16:10 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: lpieralisi, kw, bhelgaas, jingoohan1, cassel, robh, linux-pci, linux-kernel On 2025/5/2 23:36, Manivannan Sadhasivam wrote: > On Tue, Apr 29, 2025 at 01:10:24AM +0800, Hans Zhang wrote: >> 1. PCI: dwc: Standardize link status check to return bool. >> 2. PCI: mobiveil: Refactor link status check. >> 3. PCI: cadence: Simplify j721e link status check. >> > > Thanks for the cleanup. Looks good to me except the redundancy conversion that > Niklas noted. So with that change, > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Dear Mani, Thank you very much for your reply. I have sent version v2 to resolve Niklas' review opinions. Best regards, Hans > - Mani > >> Hans Zhang (3): >> PCI: dwc: Standardize link status check to return bool. >> PCI: mobiveil: Refactor link status check. >> PCI: cadence: Simplify j721e link status check. >> >> drivers/pci/controller/cadence/pci-j721e.c | 6 +----- >> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- >> drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- >> drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- >> drivers/pci/controller/dwc/pci-meson.c | 6 +++--- >> drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++--- >> drivers/pci/controller/dwc/pcie-designware.c | 2 +- >> drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- >> drivers/pci/controller/dwc/pcie-histb.c | 9 +++------ >> drivers/pci/controller/dwc/pcie-keembay.c | 2 +- >> drivers/pci/controller/dwc/pcie-kirin.c | 7 ++----- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- >> drivers/pci/controller/dwc/pcie-qcom.c | 2 +- >> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- >> drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++----- >> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- >> drivers/pci/controller/dwc/pcie-uniphier.c | 2 +- >> drivers/pci/controller/dwc/pcie-visconti.c | 2 +- >> drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 9 ++------- >> drivers/pci/controller/mobiveil/pcie-mobiveil.h | 2 +- >> 21 files changed, 34 insertions(+), 53 deletions(-) >> >> >> base-commit: 286ed198b899739862456f451eda884558526a9d >> -- >> 2.25.1 >> > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-05-02 16:11 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-04-28 17:10 [PATCH 0/3] Standardize link status check to return bool Hans Zhang 2025-04-28 17:10 ` [PATCH 1/3] PCI: dwc: " Hans Zhang 2025-04-29 8:05 ` Niklas Cassel 2025-04-29 8:21 ` Hans Zhang 2025-04-28 17:10 ` [PATCH 2/3] PCI: mobiveil: Refactor link status check Hans Zhang 2025-04-28 17:10 ` [PATCH 3/3] PCI: cadence: Simplify j721e " Hans Zhang 2025-05-02 15:36 ` [PATCH 0/3] Standardize link status check to return bool Manivannan Sadhasivam 2025-05-02 16:10 ` Hans Zhang
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