Re: [PATCH v2 00/11] iommu/arm-smmu-v3: Add PRI support

[Nicolin Chen <nicolinc@nvidia.com>]

On Fri, Jun 26, 2026 at 08:24:31PM +0530, harsha.v@oss.qualcomm.com wrote:
> One thing I noticed while reviewing: when arm_smmu_priq_thread() detects
> PRIQ overflow, partial faults (non-LAST pages stored via
> report_partial_fault()) whose LAST page was lost in the overflow remain
> permanently in iopf_param->partial. This is a monotonic memory leak —
> it grows with each overflow event.
> 
> Intel VT-d handles this in prq_event_thread() (drivers/iommu/intel/prq.c):
>     if (head == tail) {
>         iopf_queue_discard_partial(iommu->iopf_queue);
>         writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG);
>     }
> 
> iopf_queue_discard_partial() was written for exactly this scenario.
> Could we add the same here arm_smmu_priq_thread()
> (drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c) ?
> 
>     if (queue_sync_prod_in(q) == -EOVERFLOW) {
>         dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n");
> +       iopf_queue_discard_partial(smmu->evtq.iopf);
>     }
> 
> At this point all surviving entries have already been consumed by the
> loop above, so discarding unconditionally is safe — implicitly matching
> Intel's "head == tail" guard.

I will fold it in.

Thanks!
Nicolin