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From: Inochi Amaoto <inochiama@gmail.com>
To: "Alex Elder" <elder@riscstar.com>,
	"Inochi Amaoto" <inochiama@gmail.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Yixun Lan" <dlan@kernel.org>, "Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Christian Bruel" <christian.bruel@foss.st.com>,
	"Frank Li" <Frank.Li@nxp.com>, "Nam Cao" <namcao@linutronix.de>,
	"Qiang Yu" <qiang.yu@oss.qualcomm.com>,
	"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Xincheng Zhang" <zhangxincheng@ultrarisc.com>,
	"Siddharth Vadapalli" <s-vadapalli@ti.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Vidya Sagar" <vidyas@nvidia.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev,  Yixun Lan <dlan@gentoo.org>,
	Longbin Li <looong.bin@gmail.com>
Subject: Re: [PATCH v4 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller
Date: Sun, 12 Jul 2026 13:43:33 +0800	[thread overview]
Message-ID: <alMpUW6902TC5T4a@inochi.infowork> (raw)
In-Reply-To: <58948c74-0990-449e-8eee-88cbb38db7e7@riscstar.com>

On Fri, Jul 10, 2026 at 11:01:38AM -0500, Alex Elder wrote:
> On 7/8/26 11:00 PM, Inochi Amaoto wrote:
> > Add binding support for the PCIe controller on the SpacemiT K3 SoC.
> > This controller is almost a standard Synopsys DesignWare PCIe IP,
> > with some extra link and reset state control.
> > 
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> 
> This looks OK to me.  What I see is that K3 does not require
> the interrupts and interrupt-names properties, allows up to
> six PHYs (not just one), and adds a dbi2 register that is not
> used by K1.
> 
> I might have missed it, but I don't see where the dbi2 register
> is used by the K3 code you have added.  In pcie-designware.c,
> I see that if no "dbi2" resource is found, memory at offset
> 4096 from the "dbi" base is used.  Does that apply for K3?
> If so, maybe there's no need to define dbi2.
> 
> 					-Alex
> 

Weird, I have found the following logic in dw_pcie_get_resources()
of pcie-designware.c

```
	/* DBI2 is mainly useful for the endpoint controller */
	if (!pci->dbi_base2) {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
		if (res) {
			pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res);
			if (IS_ERR(pci->dbi_base2))
				return PTR_ERR(pci->dbi_base2);
		} else {
			pci->dbi_base2 = pci->dbi_base + SZ_4K;
		}
	}
```

Regards,
Inochi

> > ---
> >   .../bindings/pci/spacemit,k1-pcie-host.yaml   | 50 ++++++++++++++++---
> >   1 file changed, 43 insertions(+), 7 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> > index c4c00b5fcdc0..54817d6fd9af 100644
> > --- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> > +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> > @@ -14,26 +14,29 @@ description: >
> >     PCIe IP.  The controller uses the DesignWare built-in MSI interrupt
> >     controller, and supports 256 MSIs.
> > -allOf:
> > -  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> > -
> >   properties:
> >     compatible:
> > -    const: spacemit,k1-pcie
> > +    enum:
> > +      - spacemit,k1-pcie
> > +      - spacemit,k3-pcie
> >     reg:
> > +    minItems: 4
> >       items:
> >         - description: DesignWare PCIe registers
> >         - description: ATU address space
> >         - description: PCIe configuration space
> >         - description: Link control registers
> > +      - description: Data Bus Interface (DBI) shadow registers.
> >     reg-names:
> > +    minItems: 4
> >       items:
> >         - const: dbi
> >         - const: atu
> >         - const: config
> >         - const: link
> > +      - const: dbi2
> >     clocks:
> >       items:
> > @@ -66,6 +69,8 @@ properties:
> >     interrupt-names:
> >       const: msi
> > +  msi-parent: true
> > +
> >     spacemit,apmu:
> >       $ref: /schemas/types.yaml#/definitions/phandle-array
> >       description:
> > @@ -84,7 +89,8 @@ patternProperties:
> >       properties:
> >         phys:
> > -        maxItems: 1
> > +        minItems: 1
> > +        maxItems: 6
> >         vpcie3v3-supply:
> >           description:
> > @@ -96,13 +102,43 @@ patternProperties:
> >       unevaluatedProperties: false
> > +allOf:
> > +  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: spacemit,k1-pcie
> > +    then:
> > +      properties:
> > +        reg:
> > +          maxItems: 4
> > +
> > +        reg-names:
> > +          maxItems: 4
> > +
> > +      patternProperties:
> > +        '^pcie@':
> > +          properties:
> > +            phys:
> > +              maxItems: 1
> > +
> > +      required:
> > +        - interrupts
> > +        - interrupt-names
> > +    else:
> > +      properties:
> > +        reg:
> > +          minItems: 5
> > +
> > +        reg-names:
> > +          minItems: 5
> > +
> >   required:
> >     - clocks
> >     - clock-names
> >     - resets
> >     - reset-names
> > -  - interrupts
> > -  - interrupt-names
> >     - spacemit,apmu
> >   unevaluatedProperties: false
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-07-12  5:44 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-09  4:00 [PATCH v4 0/6] riscv: spacemit: Add PCIe RC controller support for K3 Inochi Amaoto
2026-07-09  4:00 ` [PATCH v4 1/6] PCI: spacemit-k1: Add device data support Inochi Amaoto
2026-07-09  4:05   ` sashiko-bot
2026-07-09  7:09   ` Andy Shevchenko
2026-07-10 16:01   ` Alex Elder
2026-07-12  7:38     ` Inochi Amaoto
2026-07-09  4:00 ` [PATCH v4 2/6] PCI: spacemit-k1: Add multiple PHY handles support Inochi Amaoto
2026-07-09  4:09   ` sashiko-bot
2026-07-09  7:16   ` Andy Shevchenko
2026-07-10  1:57     ` Inochi Amaoto
2026-07-10  8:07       ` Andy Shevchenko
2026-07-10 10:55         ` Inochi Amaoto
2026-07-10 12:42           ` Alex Elder
2026-07-11 13:01             ` Andy Shevchenko
2026-07-11 12:44           ` Andy Shevchenko
2026-07-12  5:41             ` Inochi Amaoto
2026-07-12  9:35               ` Andy Shevchenko
2026-07-12 10:04                 ` Inochi Amaoto
2026-07-10 12:51     ` Alex Elder
2026-07-11 13:04       ` Andy Shevchenko
2026-07-10 16:01   ` Alex Elder
2026-07-12  7:27     ` Inochi Amaoto
2026-07-09  4:00 ` [PATCH v4 3/6] PCI: spacemit-k1: Add device id update helper Inochi Amaoto
2026-07-09  4:06   ` sashiko-bot
2026-07-10 16:01   ` Alex Elder
2026-07-12  7:32     ` Inochi Amaoto
2026-07-09  4:00 ` [PATCH v4 4/6] dt-bindings: PCI: snps,dw-pcie: Add msi-parent for MSI handle check Inochi Amaoto
2026-07-09  4:06   ` sashiko-bot
2026-07-10 16:01   ` Alex Elder
2026-07-09  4:00 ` [PATCH v4 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller Inochi Amaoto
2026-07-09  4:09   ` sashiko-bot
2026-07-10 16:01   ` Alex Elder
2026-07-12  5:43     ` Inochi Amaoto [this message]
2026-07-09  4:00 ` [PATCH v4 6/6] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support Inochi Amaoto
2026-07-09  4:12   ` sashiko-bot
2026-07-09  7:21   ` Andy Shevchenko
2026-07-12  5:45     ` Inochi Amaoto
2026-07-10 16:01   ` Alex Elder
2026-07-12  7:22     ` Inochi Amaoto

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