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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
	Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Cc: cros-qcom-dts-watchers@chromium.org,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konradybcio@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com,
	quic_mrana@quicinc.com, mmareddy@quicinc.com,
	"Krishna chaitanya chundru" <quic_krichai@quicinc.com>
Subject: Re: [PATCH v3 2/4] PCI: dwc: Add ECAM support with iATU configuration
Date: Tue, 28 Jan 2025 13:53:21 +0100	[thread overview]
Message-ID: <b074baa0-07c5-450d-8531-e2b1d706df0b@oss.qualcomm.com> (raw)
In-Reply-To: <20250124061237.he34clwukqwzqx2t@thinkpad>

On 24.01.2025 7:12 AM, Manivannan Sadhasivam wrote:
> On Tue, Jan 21, 2025 at 02:32:20PM +0530, Krishna Chaitanya Chundru wrote:
>> The current implementation requires iATU for every configuration
>> space access which increases latency & cpu utilization.
>>
>> Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature,
>> which shifts/maps the BDF (bits [31:16] of the third header DWORD, which
>> would be matched against the Base and Limit addresses) of the incoming
>> CfgRd0/CfgWr0 down to bits[27:12]of the translated address.
>>
>> Configuring iATU in config shift feature enables ECAM feature to access the
>> config space, which avoids iATU configuration for every config access.
>>
>> Add "ctrl2" into struct dw_pcie_ob_atu_cfg  to enable config shift feature.
>>
>> As DBI comes under config space, this avoids remapping of DBI space
>> separately. Instead, it uses the mapped config space address returned from
>> ECAM initialization. Change the order of dw_pcie_get_resources() execution
>> to achieve this.
>>
>> Enable the ECAM feature if the config space size is equal to size required
>> to represent number of buses in the bus range property, add a function
>> which checks this. The DWC glue drivers uses this function and decide to
>> enable ECAM mode or not.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> 
> Some minor comments inline. Overall, the patch LGTM!
> 
>> ---

[...]

>> +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp)
>> +{
>> +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +	struct platform_device *pdev = to_platform_device(pci->dev);
>> +	struct resource *config_res, *bus_range;
>> +	u64 bus_config_space_count;
>> +
>> +	bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;
>> +	if (!bus_range)
>> +		return false;
>> +
>> +	config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
>> +	if (!config_res)
>> +		return false;
>> +
>> +	bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT;
>> +
>> +	return bus_config_space_count >= resource_size(bus_range);
> 
> return !!(bus_config_space_count >= resource_size(bus_range));

You made me think that there's some weird interaction here, but C99 says

"Each of the operators < (less than), > (greater than), <= (less than or equal to),
and >= (greater than or equal to) shall yield 1 if the specified relation is true and
0 if it is false.89) The result has type int"

so I'm not sure this is necessary

Konrad

  reply	other threads:[~2025-01-28 12:53 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-21  9:02 [PATCH v3 0/4] PCI: dwc: Add ECAM support with iATU configuration Krishna Chaitanya Chundru
2025-01-21  9:02 ` [PATCH v3 1/4] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature Krishna Chaitanya Chundru
2025-01-24  5:40   ` Manivannan Sadhasivam
2025-01-21  9:02 ` [PATCH v3 2/4] PCI: dwc: Add ECAM support with iATU configuration Krishna Chaitanya Chundru
2025-01-24  6:12   ` Manivannan Sadhasivam
2025-01-28 12:53     ` Konrad Dybcio [this message]
2025-01-21  9:02 ` [PATCH v3 3/4] PCI: dwc: Reduce DT reads by allocating host bridge via DWC glue driver Krishna Chaitanya Chundru
2025-01-24  6:18   ` Manivannan Sadhasivam
2025-01-24  8:26     ` Krishna Chaitanya Chundru
2025-01-24  9:36       ` Manivannan Sadhasivam
2025-01-21  9:02 ` [PATCH v3 4/4] PCI: qcom: Enable ECAM feature Krishna Chaitanya Chundru
2025-01-24  6:58   ` Manivannan Sadhasivam
2025-01-24  8:21     ` Krishna Chaitanya Chundru

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