Re: [PATCH] PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 11/26/25 9:17 AM, Manivannan Sadhasivam wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> 
> Though I couldn't confirm the ASPM L0s support with the Qcom hardware team,
> bug report from Dmitry suggests that L0s is broken on this legacy SoC.
> Hence, clear the L0s CAP for the Root Ports in this SoC.

FWIW if we trust the downstream DT, we have this hunk:

arch/arm64/boot/dts/qcom/msm8996.dtsi
1431:           qcom,l1-supported;
1432:           qcom,l1ss-supported;
1586:           qcom,l1-supported;
1587:           qcom,l1ss-supported;
1739:           qcom,l1-supported;
1740:           qcom,l1ss-supported;

But also funnily enough, msm8996auto boards specifically manually
do a /delete-property/ on those..

(there exists one 'qcom,l0s-supported', but it's NOT set for 8996, 98,
or 845)

On msm-4.14, this became "qcom,no-l0s/l1/l1ss-supported". This forbids L0s
on at least 8150 and 8250.

Later, both hosts on SM8350 and SM8450-PCIe0 (not 1) forbid L0s.

SM8350-PCIe0 sets 'qcom,l1ss-sleep-disable' which influences some RPMh
things, but also prevents some clock ops wrt the CLKREF source

There's probably more platforms affected, this was a quick grep.

Konrad