Re: [PATCH 0/3] PCI: Add Secondary Bus Reset (SBR) support for CXL

[Dave Jiang <dave.jiang@intel.com>]

On 3/12/24 12:46 AM, Lukas Wunner wrote:
> On Mon, Mar 11, 2024 at 01:39:52PM -0700, Dave Jiang wrote:
>> Patch 1:
>> Add check to PCI bus_reset path for CXL device and return with error if "Unmask
>> SBR" bit is set to 0. This allows user to realize that SBR is masked for this
>> CXL device. However, if the user sets the "Unmask SBR" bit via a tool such as
>> setpci, then the bus_reset will proceed.
> 
> So is the point of patch 1 only to inform the user that the SBR has
> no effect?  Or does the SBR have any negative side effects that you
> want to avoid (e.g. due to the config space save/restore)?
> 
> If you only want to inform the user, then this functionality could
> live in a ->reset_prepare() callback exposed by the cxl subsystem
> and the pci subsystem wouldn't have to be touched at all.

Patch 1 is to inform the user that SBR has no effect. The user needs to be informed via direct errno feedback that reset is masked and isn't going to happen. In this [1] response, I believe Bjorn wanted pci_reset_function() to fail. ->reset_prepare() is only helpful if the cxl_pci driver is loaded. CXL mem devices can be programmed by the BIOS and be active without CXL driver being loaded. Also, cxl_pci only picks up PCI_CLASS_MEMORY_CXL. So other CXL devices would not be managed by this driver.

[1]: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/


> 
> Thanks,
> 
> Lukas