From: Hans Zhang <18255117159@163.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
bhelgaas@google.com, jingoohan1@gmail.com,
thomas.richard@bootlin.com, linux-pci@vger.kernel.org,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [v6 3/5] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities
Date: Tue, 25 Mar 2025 22:47:42 +0800 [thread overview]
Message-ID: <de6ce71c-ba82-496e-9c72-7c9c61b37906@163.com> (raw)
In-Reply-To: <f2725090-e199-493d-9ae3-e807d65f647b@163.com>
On 2025/3/25 20:16, Hans Zhang wrote:
>>>>>> I'm really wondering why the read config function is provided
>>>>>> directly
>>>>>> as
>>>>>> an argument. Shouldn't struct pci_host_bridge have some ops that can
>>>>>> read
>>>>>> config so wouldn't it make much more sense to pass it and use the
>>>>>> func
>>>>>> from there? There seems to ops in pci_host_bridge that has read(),
>>>>>> does
>>>>>> that work? If not, why?
>>>>>>
>>>>>
>>>>> No effect.
>>>>
>>>> I'm not sure what you meant?
>>>>
>>>>> Because we need to get the offset of the capability before PCIe
>>>>> enumerates the device.
>>>>
>>>> Is this to say it is needed before the struct pci_host_bridge is
>>>> created?
>>>>
>>>>> I originally added a separate find capability related
>>>>> function for CDNS in the following patch. It's also copied directly
>>>>> from
>>>>> DWC.
>>>>> Mani felt there was too much duplicate code and also suggested
>>>>> passing a
>>>>> callback function that could manipulate the registers of the root
>>>>> port of
>>>>> DWC
>>>>> or CDNS.
>>>>
>>>> I very much like the direction this patchset is moving (moving shared
>>>> part of controllers code to core), I just feel this doesn't go far
>>>> enough
>>>> when it's passing function pointer to the read function.
>>>>
>>>> I admit I've never written a controller driver so perhaps there's
>>>> something detail I lack knowledge of but I'd want to understand why
>>>> struct pci_ops (which exists both in pci_host_bridge and pci_bus)
>>>> cannot
>>>> be used?
>>>>
>>>
>>>
>>> I don't know if the following code can make it clear to you.
>>>
>>> static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
>>> .host_init = qcom_pcie_host_init,
>>> pcie->cfg->ops->post_init(pcie);
>>> qcom_pcie_post_init_2_3_3
>>> dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>> };
>>>
>>> int dw_pcie_host_init(struct dw_pcie_rp *pp)
>>> bridge = devm_pci_alloc_host_bridge(dev, 0);
>>
>> It does this almost immediately:
>>
>> bridge->ops = &dw_pcie_ops;
>>
>> Can we like add some function into those ops such that the necessary read
>> can be performed? Like .early_root_config_read or something like that?
>>
>> Then the host bridge capability finder can input struct pci_host_bridge
>> *host_bridge and can do
>> host_bridge->ops->early_root_cfg_read(host_bridge,
>> ...). That would already be a big win over passing the read function
>> itself as a pointer.
>>
>> Hopefully having such a function in the ops would allow moving other
>> common controller driver functionality into PCI core as well as it would
>> abstract the per controller read function (for the time before everything
>> is fully instanciated).
>>
>> Is that a workable approach?
>>
>
> I'll try to add and test it in your way first.
>
> Another problem here is that I've seen some drivers invoke
> dw_pcie_find_*capability before if (pp->ops->init) {. When I confirm it,
> or I'll see if I can cover all the issues.
>
> If I pass the test, I will provide the temporary patch here, please
> check whether it is OK, and then submit the next version. If not, we'll
> discuss it.
>
Hi Ilpo,
Another question comes to mind:
If working in EP mode, devm_pci_alloc_host_bridge will not be executed
and there will be no struct pci_host_bridge.
Don't know if you have anything to add?
> Thank you very much for your advice.
>
>>> if (pp->ops->host_init)
>>> pp->ops = &qcom_pcie_dw_ops; // qcom here needs to find capability
>>>
>>> pci_host_probe(bridge); // pcie enumerate flow
>>> pci_scan_root_bus_bridge(bridge);
>>> pci_register_host_bridge(bridge);
>>> bus->ops = bridge->ops; // Only pci bus ops can be used
>>>
>>>
Best regards,
Hans
next prev parent reply other threads:[~2025-03-25 14:48 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-23 16:48 [v6 0/5] Introduce generic capability search functions Hans Zhang
2025-03-23 16:48 ` [v6 1/5] PCI: " Hans Zhang
2025-03-24 13:28 ` Ilpo Järvinen
2025-03-24 14:39 ` Hans Zhang
2025-03-24 14:52 ` Ilpo Järvinen
2025-03-25 2:58 ` Hans Zhang
2025-03-27 16:57 ` Manivannan Sadhasivam
2025-03-28 9:41 ` Hans Zhang
2025-03-27 16:58 ` Manivannan Sadhasivam
2025-03-28 9:42 ` Hans Zhang
2025-03-23 16:48 ` [v6 2/5] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Hans Zhang
2025-03-23 16:48 ` [v6 3/5] PCI: cadence: " Hans Zhang
2025-03-23 18:33 ` kernel test robot
2025-03-24 1:07 ` Hans Zhang
2025-03-23 19:26 ` kernel test robot
2025-03-24 1:08 ` Hans Zhang
2025-03-24 13:44 ` Ilpo Järvinen
2025-03-24 14:29 ` Hans Zhang
2025-03-24 15:02 ` Ilpo Järvinen
2025-03-25 2:59 ` Hans Zhang
2025-03-25 11:15 ` Ilpo Järvinen
2025-03-25 12:16 ` Hans Zhang
2025-03-25 14:47 ` Hans Zhang [this message]
2025-03-25 15:18 ` Ilpo Järvinen
2025-03-25 15:37 ` Hans Zhang
2025-03-28 10:33 ` Hans Zhang
2025-03-28 11:42 ` Ilpo Järvinen
2025-03-29 16:03 ` Hans Zhang
2025-03-31 16:39 ` Ilpo Järvinen
2025-04-01 13:20 ` Hans Zhang
2025-03-23 16:48 ` [v6 4/5] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode Hans Zhang
2025-03-23 16:48 ` [v6 5/5] MAINTAINERS: Add entry for PCI host controller helpers Hans Zhang
2025-03-27 17:01 ` Manivannan Sadhasivam
2025-03-28 10:36 ` Hans Zhang
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