* [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro
@ 2025-06-07 15:55 Hans Zhang
2025-06-07 15:55 ` [PATCH v2 1/3] PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro Hans Zhang
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Hans Zhang @ 2025-06-07 15:55 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, kwilczynski, mani, ilpo.jarvinen,
jingoohan1
Cc: robh, linux-pci, linux-kernel, Hans Zhang
This series standardizes PCIe link speed handling across multiple drivers
by introducing a common conversion macro PCIE_SPEED2LNKCTL2_TLS(). The
changes eliminate redundant speed-to-register mappings and simplify code
maintenance:
The refactoring improves code consistency and reduces conditional
branching, while maintaining full backward compatibility with existing
speed settings.
---
Changes for v2:
- s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
- The patch commit message were modified.
---
Hans Zhang (3):
PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro
PCI: dwc: Simplify link speed configuration with macro
PCI/bwctrl: Replace legacy speed conversion with shared macro
drivers/pci/controller/dwc/pcie-designware.c | 18 +++---------------
drivers/pci/pci.h | 9 +++++++++
drivers/pci/pcie/bwctrl.c | 19 +------------------
3 files changed, 13 insertions(+), 33 deletions(-)
base-commit: ec7714e4947909190ffb3041a03311a975350fe0
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro
2025-06-07 15:55 [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Hans Zhang
@ 2025-06-07 15:55 ` Hans Zhang
2025-06-07 15:55 ` [PATCH v2 2/3] PCI: dwc: Simplify link speed configuration with macro Hans Zhang
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Hans Zhang @ 2025-06-07 15:55 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, kwilczynski, mani, ilpo.jarvinen,
jingoohan1
Cc: robh, linux-pci, linux-kernel, Hans Zhang
Introduce PCIE_SPEED2LNKCTL2_TLS() macro to standardize the conversion
between PCIe speed enumerations and LNKCTL2_TLS register values. This
centralizes speed-to-register mapping logic, eliminating duplicated
conversion code across multiple drivers.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/pci.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 12215ee72afb..b5a3ce6c239b 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -419,6 +419,15 @@ void pci_bus_put(struct pci_bus *bus);
(lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
PCI_SPEED_UNKNOWN)
+#define PCIE_SPEED2LNKCTL2_TLS(speed) \
+ ((speed) == PCIE_SPEED_2_5GT ? PCI_EXP_LNKCTL2_TLS_2_5GT : \
+ (speed) == PCIE_SPEED_5_0GT ? PCI_EXP_LNKCTL2_TLS_5_0GT : \
+ (speed) == PCIE_SPEED_8_0GT ? PCI_EXP_LNKCTL2_TLS_8_0GT : \
+ (speed) == PCIE_SPEED_16_0GT ? PCI_EXP_LNKCTL2_TLS_16_0GT : \
+ (speed) == PCIE_SPEED_32_0GT ? PCI_EXP_LNKCTL2_TLS_32_0GT : \
+ (speed) == PCIE_SPEED_64_0GT ? PCI_EXP_LNKCTL2_TLS_64_0GT : \
+ 0)
+
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] PCI: dwc: Simplify link speed configuration with macro
2025-06-07 15:55 [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Hans Zhang
2025-06-07 15:55 ` [PATCH v2 1/3] PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro Hans Zhang
@ 2025-06-07 15:55 ` Hans Zhang
2025-06-07 15:55 ` [PATCH v2 3/3] PCI/bwctrl: Replace legacy speed conversion with shared macro Hans Zhang
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Hans Zhang @ 2025-06-07 15:55 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, kwilczynski, mani, ilpo.jarvinen,
jingoohan1
Cc: robh, linux-pci, linux-kernel, Hans Zhang
Replace switch-case based speed-to-register conversion in DesignWare
driver with the newly introduced PCIE_SPEED2LNKCTL2_TLS() macro.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 18 +++---------------
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 4d794964fa0f..da91b57ad744 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -768,24 +768,12 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
- switch (pcie_link_speed[pci->max_link_speed]) {
- case PCIE_SPEED_2_5GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
- break;
- case PCIE_SPEED_5_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
- break;
- case PCIE_SPEED_8_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
- break;
- case PCIE_SPEED_16_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
- break;
- default:
+ link_speed = pcie_link_speed[pci->max_link_speed];
+ link_speed = PCIE_SPEED2LNKCTL2_TLS(link_speed);
+ if (link_speed == 0) {
/* Use hardware capability */
link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
- break;
}
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] PCI/bwctrl: Replace legacy speed conversion with shared macro
2025-06-07 15:55 [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Hans Zhang
2025-06-07 15:55 ` [PATCH v2 1/3] PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro Hans Zhang
2025-06-07 15:55 ` [PATCH v2 2/3] PCI: dwc: Simplify link speed configuration with macro Hans Zhang
@ 2025-06-07 15:55 ` Hans Zhang
2025-06-19 13:26 ` [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Manivannan Sadhasivam
2025-06-24 15:13 ` Hans Zhang
4 siblings, 0 replies; 6+ messages in thread
From: Hans Zhang @ 2025-06-07 15:55 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, kwilczynski, mani, ilpo.jarvinen,
jingoohan1
Cc: robh, linux-pci, linux-kernel, Hans Zhang
Remove obsolete pci_bus_speed2lnkctl2() function and utilize the common
PCIE_SPEED2LNKCTL2_TLS() macro instead.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/pcie/bwctrl.c | 19 +------------------
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
index 36f939f23d34..5afc1f45c444 100644
--- a/drivers/pci/pcie/bwctrl.c
+++ b/drivers/pci/pcie/bwctrl.c
@@ -53,23 +53,6 @@ static bool pcie_valid_speed(enum pci_bus_speed speed)
return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
}
-static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
-{
- static const u8 speed_conv[] = {
- [PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
- [PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
- [PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
- [PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
- [PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
- [PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
- };
-
- if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
- return 0;
-
- return speed_conv[speed];
-}
-
static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
{
return __fls(supported_speeds);
@@ -91,7 +74,7 @@ static u16 pcie_bwctrl_select_speed(struct pci_dev *port, enum pci_bus_speed spe
u8 desired_speeds, supported_speeds;
struct pci_dev *dev;
- desired_speeds = GENMASK(pci_bus_speed2lnkctl2(speed_req),
+ desired_speeds = GENMASK(PCIE_SPEED2LNKCTL2_TLS(speed_req),
__fls(PCI_EXP_LNKCAP2_SLS_2_5GB));
supported_speeds = port->supported_speeds;
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro
2025-06-07 15:55 [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Hans Zhang
` (2 preceding siblings ...)
2025-06-07 15:55 ` [PATCH v2 3/3] PCI/bwctrl: Replace legacy speed conversion with shared macro Hans Zhang
@ 2025-06-19 13:26 ` Manivannan Sadhasivam
2025-06-24 15:13 ` Hans Zhang
4 siblings, 0 replies; 6+ messages in thread
From: Manivannan Sadhasivam @ 2025-06-19 13:26 UTC (permalink / raw)
To: Hans Zhang
Cc: bhelgaas, lpieralisi, kw, kwilczynski, ilpo.jarvinen, jingoohan1,
robh, linux-pci, linux-kernel
On Sat, Jun 07, 2025 at 11:55:42PM +0800, Hans Zhang wrote:
> This series standardizes PCIe link speed handling across multiple drivers
> by introducing a common conversion macro PCIE_SPEED2LNKCTL2_TLS(). The
> changes eliminate redundant speed-to-register mappings and simplify code
> maintenance:
>
> The refactoring improves code consistency and reduces conditional
> branching, while maintaining full backward compatibility with existing
> speed settings.
>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
- Mani
> ---
> Changes for v2:
> - s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
> - The patch commit message were modified.
> ---
>
> Hans Zhang (3):
> PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro
> PCI: dwc: Simplify link speed configuration with macro
> PCI/bwctrl: Replace legacy speed conversion with shared macro
>
> drivers/pci/controller/dwc/pcie-designware.c | 18 +++---------------
> drivers/pci/pci.h | 9 +++++++++
> drivers/pci/pcie/bwctrl.c | 19 +------------------
> 3 files changed, 13 insertions(+), 33 deletions(-)
>
>
> base-commit: ec7714e4947909190ffb3041a03311a975350fe0
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro
2025-06-07 15:55 [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Hans Zhang
` (3 preceding siblings ...)
2025-06-19 13:26 ` [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Manivannan Sadhasivam
@ 2025-06-24 15:13 ` Hans Zhang
4 siblings, 0 replies; 6+ messages in thread
From: Hans Zhang @ 2025-06-24 15:13 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, kwilczynski, mani, ilpo.jarvinen,
jingoohan1
Cc: robh, linux-pci, linux-kernel
Dear Ilpo,
Gentle ping.
Best regards,
Hans
On 2025/6/7 23:55, Hans Zhang wrote:
> This series standardizes PCIe link speed handling across multiple drivers
> by introducing a common conversion macro PCIE_SPEED2LNKCTL2_TLS(). The
> changes eliminate redundant speed-to-register mappings and simplify code
> maintenance:
>
> The refactoring improves code consistency and reduces conditional
> branching, while maintaining full backward compatibility with existing
> speed settings.
>
> ---
> Changes for v2:
> - s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
> - The patch commit message were modified.
> ---
>
> Hans Zhang (3):
> PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro
> PCI: dwc: Simplify link speed configuration with macro
> PCI/bwctrl: Replace legacy speed conversion with shared macro
>
> drivers/pci/controller/dwc/pcie-designware.c | 18 +++---------------
> drivers/pci/pci.h | 9 +++++++++
> drivers/pci/pcie/bwctrl.c | 19 +------------------
> 3 files changed, 13 insertions(+), 33 deletions(-)
>
>
> base-commit: ec7714e4947909190ffb3041a03311a975350fe0
^ permalink raw reply [flat|nested] 6+ messages in thread
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2025-06-07 15:55 [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Hans Zhang
2025-06-07 15:55 ` [PATCH v2 1/3] PCI: Add PCIE_SPEED2LNKCTL2_TLS conversion macro Hans Zhang
2025-06-07 15:55 ` [PATCH v2 2/3] PCI: dwc: Simplify link speed configuration with macro Hans Zhang
2025-06-07 15:55 ` [PATCH v2 3/3] PCI/bwctrl: Replace legacy speed conversion with shared macro Hans Zhang
2025-06-19 13:26 ` [PATCH v2 0/3] PCIe: Refactor link speed configuration with unified macro Manivannan Sadhasivam
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