Re: [PATCH v3 2/2] PCI: qcom: Avoid DBI and ATU register space mirror to BAR/MMIO region

[Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>]

Hi Manivannan,

Thanks for the review comments.

On 7/24/2024 7:10 AM, Manivannan Sadhasivam wrote:
> Subject:
> 
> PCI: qcom: Disable mirroring of DBI and iATU register space in BAR/MMIO region
> 

ACK. I will update it in the next patch.

> On Tue, Jul 23, 2024 at 07:27:19PM -0700, Prudhvi Yarlagadda wrote:
>> PARF hardware block which is a wrapper on top of DWC PCIe controller
>> mirrors the DBI and ATU register space. It uses PARF_SLV_ADDR_SPACE_SIZE
>> register to get the size of the memory block to be mirrored and uses
>> PARF_DBI_BASE_ADDR, PARF_ATU_BASE_ADDR registers to determine the base
>> address of DBI and ATU space inside the memory block that is being
>> mirrored.
>>
>> When a memory region which is located above the SLV_ADDR_SPACE_SIZE
>> boundary is used for BAR region then there could be an overlap of DBI and
>> ATU address space that is getting mirrored and the BAR region. This
>> results in DBI and ATU address space contents getting updated when a PCIe
>> function driver tries updating the BAR/MMIO memory region. Reference
>> memory map of the PCIe memory region with DBI and ATU address space
>> overlapping BAR region is as below.
>>
>>                         |---------------|
>>                         |               |
>>                         |               |
>>         ------- --------|---------------|
>>            |       |    |---------------|
>>            |       |    |       DBI     |
>>            |       |    |---------------|---->DBI_BASE_ADDR
>>            |       |    |               |
>>            |       |    |               |
>>            |    PCIe    |               |---->2*SLV_ADDR_SPACE_SIZE
>>            |    BAR/MMIO|---------------|
>>            |    Region  |       ATU     |
>>            |       |    |---------------|---->ATU_BASE_ADDR
>>            |       |    |               |
>>         PCIe       |    |---------------|
>>         Memory     |    |       DBI     |
>>         Region     |    |---------------|---->DBI_BASE_ADDR
>>            |       |    |               |
>>            |    --------|               |
>>            |            |               |---->SLV_ADDR_SPACE_SIZE
>>            |            |---------------|
>>            |            |       ATU     |
>>            |            |---------------|---->ATU_BASE_ADDR
>>            |            |               |
>>            |            |---------------|
>>            |            |       DBI     |
>>            |            |---------------|---->DBI_BASE_ADDR
>>            |            |               |
>>            |            |               |
>>         ----------------|---------------|
>>                         |               |
>>                         |               |
>>                         |               |
>>                         |---------------|
>>
>> Currently memory region beyond the SLV_ADDR_SPACE_SIZE boundary is not
>> used for BAR region which is why the above mentioned issue is not
>> encountered. This issue is discovered as part of internal testing when we
>> tried moving the BAR region beyond the SLV_ADDR_SPACE_SIZE boundary. Hence
>> we are trying to fix this.
>>
>> As PARF hardware block mirrors DBI and ATU register space after every
>> PARF_SLV_ADDR_SPACE_SIZE (default 0x1000000) boundary multiple, write
>> U32_MAX (all 0xFF's) to PARF_SLV_ADDR_SPACE_SIZE register to avoid
>> mirroring DBI and ATU to BAR/MMIO region. Write the physical base address
>> of DBI and ATU register blocks to PARF_DBI_BASE_ADDR (default 0x0) and
>> PARF_ATU_BASE_ADDR (default 0x1000) respectively to make sure DBI and ATU
>> blocks are at expected memory locations.
>>
>> The register offsets PARF_DBI_BASE_ADDR_V2, PARF_SLV_ADDR_SPACE_SIZE_V2
>> and PARF_ATU_BASE_ADDR are applicable for platforms that use PARF
> 
> There is no 'PARF Qcom IP', just 'Qcom IP'. Here and below.
> 

ACK. I will update it in the next patch.

>> Qcom IP rev 1.9.0, 2.7.0 and 2.9.0. PARF_DBI_BASE_ADDR_V2 and
>> PARF_SLV_ADDR_SPACE_SIZE_V2 are applicable for PARF Qcom IP rev 2.3.3.
>> PARF_DBI_BASE_ADDR and PARF_SLV_ADDR_SPACE_SIZE are applicable for PARF
>> Qcom IP rev 1.0.0, 2.3.2 and 2.4.0. Updating the init()/post_init()
> 
> Use imperative tone in commit message. s/Updating/Update
> 

ACK. I will update it in the next patch.

>> functions of the respective PARF versions to program applicable
>> PARF_DBI_BASE_ADDR, PARF_SLV_ADDR_SPACE_SIZE and PARF_ATU_BASE_ADDR
>> register offsets. And remove the unused SLV_ADDR_SPACE_SZ macro.
>>
>> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>> Reviewed-by: Mayank Rana <quic_mrana@quicinc.com>
>> ---
>>  drivers/pci/controller/dwc/pcie-qcom.c | 62 +++++++++++++++++++-------
>>  1 file changed, 45 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 0180edf3310e..6976efb8e2f0 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -45,6 +45,7 @@
>>  #define PARF_PHY_REFCLK				0x4c
>>  #define PARF_CONFIG_BITS			0x50
>>  #define PARF_DBI_BASE_ADDR			0x168
>> +#define PARF_SLV_ADDR_SPACE_SIZE		0x16C
> 
> Use lowercase for hex.
> 

ACK. I will update it in the next patch.

Thanks,
Prudhvi
> Rest LGTM! With above mentioned changes,
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> - Mani
>