From: sashiko-bot@kernel.org
To: "Koichiro Den" <den@valinux.co.jp>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds
Date: Fri, 09 Oct 2026 05:02:52 +0000 [thread overview]
Message-ID: <sashiko-outbox-164864@kernel.org> (raw)
In-Reply-To: <20261009045452.1107921-4-den@valinux.co.jp>
> The QTG _DSM expects read and write latencies in picoseconds, as
> specified in CXL 3.0, Table 9-30.
>
> The code base originally kept the latencies passed to the QTG _DSM in
> picoseconds in effect. Commit 51293c565cf4 ("cxl: Fix incorrect region
> perf data calculation") normalized CDAT and host bridge latencies to
> nanoseconds, but did not add a conversion back to picoseconds when
> constructing the _DSM input. Firmware can therefore select QTG IDs using
> understated latencies.
>
> Convert the latencies to picoseconds when constructing the _DSM input
> package. Multiply in 64 bits and reject latencies that cannot fit in the
> DWORD inputs defined by the specification.
>
> Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
> Cc: stable@vger.kernel.org
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009045452.1107921-1-den@valinux.co.jp?part=3
prev parent reply other threads:[~2026-10-09 5:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 4:54 [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Koichiro Den
2026-10-09 4:54 ` [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds Koichiro Den
2026-10-09 5:02 ` sashiko-bot
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
2026-10-09 5:01 ` sashiko-bot
2026-10-09 4:54 ` [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds Koichiro Den
2026-10-09 5:02 ` sashiko-bot [this message]
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