From: sashiko-bot@kernel.org
To: "Koichiro Den" <den@valinux.co.jp>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds
Date: Fri, 09 Oct 2026 05:02:42 +0000 [thread overview]
Message-ID: <sashiko-outbox-164863@kernel.org> (raw)
In-Reply-To: <20261009045452.1107921-2-den@valinux.co.jp>
> Commit 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
> converted CDAT latencies to nanoseconds and removed the conversion in
> cxl_region_perf_data_calculate(), but left PCIe link latencies in
> picoseconds.
>
> This inflates the FlitLatency contribution to region and node latencies
> by a factor of 1000, exposing incorrect values in sysfs. The resulting
> abstract distances can incorrectly reverse the memory tier ordering of
> nodes.
>
> Convert the FlitLatency contribution to nanoseconds before adding it to
> the access coordinates, rounding up as cdat_normalize() does.
>
> Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
> Cc: stable@vger.kernel.org
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009045452.1107921-1-den@valinux.co.jp?part=1
next prev parent reply other threads:[~2026-10-09 5:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 4:54 [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Koichiro Den
2026-10-09 4:54 ` [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds Koichiro Den
2026-10-09 5:02 ` sashiko-bot [this message]
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
2026-10-09 5:01 ` sashiko-bot
2026-10-09 15:09 ` Bjorn Helgaas
2026-10-09 4:54 ` [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds Koichiro Den
2026-10-09 5:02 ` sashiko-bot
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