* [PATCH v9 1/9] PCI: dw-rockchip: Fix LTSSM set functions
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:36 ` sashiko-bot
2026-11-05 13:33 ` [PATCH v9 2/9] PCI: dw-rockchip: Restore vpcie3v3 regulator handle Sebastian Reichel
` (8 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
Before the Rockchip PCIe driver has been switched over to the
FIELD_PREP_WM16 macro, PCIE_CLIENT_ENABLE_LTSSM and
PCIE_CLIENT_DISABLE_LTSSM were setting bits with a mask of 0xc = 0b1100,
which means BIT 2 and BIT 3. After the conversion it only sets bit 2,
with bit 3 being handled by a separate define named
PCIE_CLIENT_LD_RQ_RST_GRT. Apparently the conversion missed to make use
of this new macros resulting in the third bit not being set.
Fixes: 30e919570581 ("PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro")
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index bd86e32cc2b1..c35c5583c797 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -322,14 +322,16 @@ static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
{
- rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
- PCIE_CLIENT_GENERAL_CON);
+ u32 val = PCIE_CLIENT_ENABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT;
+
+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON);
}
static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
{
- rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
- PCIE_CLIENT_GENERAL_CON);
+ u32 val = PCIE_CLIENT_DISABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT;
+
+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON);
}
static bool rockchip_pcie_link_up(struct dw_pcie *pci)
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 2/9] PCI: dw-rockchip: Restore vpcie3v3 regulator handle
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 1/9] PCI: dw-rockchip: Fix LTSSM set functions Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:36 ` sashiko-bot
2026-11-05 13:33 ` [PATCH v9 3/9] PCI: dw-rockchip: Move devm_phy_get out of phy_init Sebastian Reichel
` (7 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
This reverts commit c930b10f17c0 ("PCI: dw-rockchip: Simplify regulator
setup with devm_regulator_get_enable_optional()"), which nicely cleaned
up the code.
The vpcie3v3 regulator handle is needed to disable the regulator during
system suspend (to be added in its own patch).
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index c35c5583c797..574d3dcfcf8b 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -113,6 +113,7 @@ struct rockchip_pcie {
unsigned int clk_cnt;
struct reset_control *rst;
struct gpio_desc *rst_gpio;
+ struct regulator *vpcie3v3;
struct irq_domain *irq_domain;
const struct rockchip_pcie_of_data *data;
bool supports_clkreq;
@@ -844,15 +845,24 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
return ret;
/* DON'T MOVE ME: must be enable before PHY init */
- ret = devm_regulator_get_enable_optional(dev, "vpcie3v3");
- if (ret < 0 && ret != -ENODEV)
- return dev_err_probe(dev, ret,
- "failed to enable vpcie3v3 regulator\n");
+ rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
+ if (IS_ERR(rockchip->vpcie3v3)) {
+ if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
+ return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
+ "failed to get vpcie3v3 regulator\n");
+ rockchip->vpcie3v3 = NULL;
+ } else {
+ ret = regulator_enable(rockchip->vpcie3v3);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to enable vpcie3v3 regulator\n");
+ }
ret = rockchip_pcie_phy_init(rockchip);
- if (ret)
- return dev_err_probe(dev, ret,
- "failed to initialize the phy\n");
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to initialize the phy\n");
+ goto disable_regulator;
+ }
ret = reset_control_deassert(rockchip->rst);
if (ret)
@@ -885,6 +895,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
deinit_phy:
rockchip_pcie_phy_deinit(rockchip);
+disable_regulator:
+ if (rockchip->vpcie3v3)
+ regulator_disable(rockchip->vpcie3v3);
return ret;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 3/9] PCI: dw-rockchip: Move devm_phy_get out of phy_init
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 1/9] PCI: dw-rockchip: Fix LTSSM set functions Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 2/9] PCI: dw-rockchip: Restore vpcie3v3 regulator handle Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:38 ` sashiko-bot
2026-11-05 13:33 ` [PATCH v9 4/9] PCI: dw-rockchip: Add helper function for enhanced LTSSM control mode Sebastian Reichel
` (6 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
By moving devm_phy_get() to the probe routine, rockchip_pcie_phy_init()
can be used to re-initialize the PCIe PHY, which is for example needed
after a system suspend/resume cycle.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 574d3dcfcf8b..a3b0fb918479 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -599,14 +599,8 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev,
static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
{
- struct device *dev = rockchip->pci.dev;
int ret;
- rockchip->phy = devm_phy_get(dev, "pcie-phy");
- if (IS_ERR(rockchip->phy))
- return dev_err_probe(dev, PTR_ERR(rockchip->phy),
- "missing PHY\n");
-
ret = phy_init(rockchip->phy);
if (ret < 0)
return ret;
@@ -858,6 +852,13 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
"failed to enable vpcie3v3 regulator\n");
}
+ rockchip->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(rockchip->phy)) {
+ ret = PTR_ERR(rockchip->phy);
+ dev_err_probe(dev, ret, "missing PHY\n");
+ goto disable_regulator;
+ }
+
ret = rockchip_pcie_phy_init(rockchip);
if (ret) {
dev_err_probe(dev, ret, "failed to initialize the phy\n");
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 4/9] PCI: dw-rockchip: Add helper function for enhanced LTSSM control mode
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (2 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 3/9] PCI: dw-rockchip: Move devm_phy_get out of phy_init Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 5/9] PCI: dw-rockchip: Add helper function for controller mode Sebastian Reichel
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
Remove code duplication and improve readability by introducing a new
function to setup the enhanced LTSSM mode.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 28 ++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index a3b0fb918479..92154a790ac0 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -683,6 +683,18 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
return IRQ_HANDLED;
}
+static void rockchip_pcie_enable_enhanced_ltssm_control_mode(struct rockchip_pcie *rockchip,
+ bool delay_link_training_after_reset)
+{
+ u32 val;
+
+ /* Enable the enhanced control mode of signal app_ltssm_enable */
+ val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1);
+ if (delay_link_training_after_reset)
+ val |= FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1);
+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
+}
+
static int rockchip_pcie_configure_rc(struct platform_device *pdev,
struct rockchip_pcie *rockchip)
{
@@ -706,9 +718,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev,
return ret;
}
- /* LTSSM enable control mode */
- val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1);
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
+ rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, false);
rockchip_pcie_writel_apb(rockchip,
PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC),
@@ -765,13 +775,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
return ret;
}
- /*
- * LTSSM enable control mode, and automatically delay link training on
- * hot reset/link-down reset.
- */
- val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1) |
- FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1);
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
+ rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, true);
rockchip_pcie_writel_apb(rockchip,
PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP),
@@ -940,9 +944,7 @@ static int rockchip_pcie_rc_reset_root_port(struct pci_host_bridge *bridge,
goto deinit_clk;
}
- /* LTSSM enable control mode */
- val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1);
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
+ rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, false);
rockchip_pcie_writel_apb(rockchip,
PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC),
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 5/9] PCI: dw-rockchip: Add helper function for controller mode
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (3 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 4/9] PCI: dw-rockchip: Add helper function for enhanced LTSSM control mode Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 6/9] PCI: dw-rockchip: Add helper function for DLL interrupts Sebastian Reichel
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
Remove code duplication and improve readability by introducing a new
function to setup the controller mode.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 92154a790ac0..07718667c225 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -695,6 +695,11 @@ static void rockchip_pcie_enable_enhanced_ltssm_control_mode(struct rockchip_pci
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
}
+static void rockchip_pcie_set_controller_mode(struct rockchip_pcie *rockchip, u32 mode)
+{
+ rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(mode), PCIE_CLIENT_GENERAL_CON);
+}
+
static int rockchip_pcie_configure_rc(struct platform_device *pdev,
struct rockchip_pcie *rockchip)
{
@@ -719,10 +724,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev,
}
rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, false);
-
- rockchip_pcie_writel_apb(rockchip,
- PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC),
- PCIE_CLIENT_GENERAL_CON);
+ rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_RC);
irq = of_irq_get_byname(dev->of_node, "legacy");
if (irq < 0)
@@ -776,10 +778,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
}
rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, true);
-
- rockchip_pcie_writel_apb(rockchip,
- PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP),
- PCIE_CLIENT_GENERAL_CON);
+ rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_EP);
rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
rockchip->pci.ep.page_size = SZ_64K;
@@ -945,10 +944,7 @@ static int rockchip_pcie_rc_reset_root_port(struct pci_host_bridge *bridge,
}
rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, false);
-
- rockchip_pcie_writel_apb(rockchip,
- PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC),
- PCIE_CLIENT_GENERAL_CON);
+ rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_RC);
ret = dw_pcie_setup_rc(pp);
if (ret) {
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 6/9] PCI: dw-rockchip: Add helper function for DLL interrupts
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (4 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 5/9] PCI: dw-rockchip: Add helper function for controller mode Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 7/9] PCI: dw-rockchip: Add pme_turn_off support Sebastian Reichel
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
Remove code duplication and improve readability by introducing a new
function to setup the DLL indicator.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 30 +++++++++++++++------------
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 07718667c225..b4f53ce86079 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -700,13 +700,26 @@ static void rockchip_pcie_set_controller_mode(struct rockchip_pcie *rockchip, u3
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(mode), PCIE_CLIENT_GENERAL_CON);
}
+static void rockchip_pcie_unmask_dll_interrupts(struct rockchip_pcie *rockchip, bool link_event)
+{
+ u32 val;
+
+ /* unmask hot reset/link-down reset event */
+ val = FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0);
+
+ /* unmask DLL link up/down event */
+ if (link_event)
+ val |= FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0);
+
+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
+}
+
static int rockchip_pcie_configure_rc(struct platform_device *pdev,
struct rockchip_pcie *rockchip)
{
struct device *dev = &pdev->dev;
struct dw_pcie_rp *pp;
int irq, ret;
- u32 val;
if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))
return -ENODEV;
@@ -748,9 +761,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev,
return ret;
}
- /* unmask hot reset/link-down reset */
- val = FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0);
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
+ rockchip_pcie_unmask_dll_interrupts(rockchip, false);
return ret;
}
@@ -760,7 +771,6 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
{
struct device *dev = &pdev->dev;
int irq, ret;
- u32 val;
if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
return -ENODEV;
@@ -800,10 +810,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev,
pci_epc_init_notify(rockchip->pci.ep.epc);
- /* unmask DLL up/down indicator and hot reset/link-down reset */
- val = FIELD_PREP_WM16(PCIE_RDLH_LINK_UP_CHGED, 0) |
- FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0);
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
+ rockchip_pcie_unmask_dll_interrupts(rockchip, true);
return ret;
}
@@ -914,7 +921,6 @@ static int rockchip_pcie_rc_reset_root_port(struct pci_host_bridge *bridge,
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
struct device *dev = rockchip->pci.dev;
- u32 val;
int ret;
dw_pcie_stop_link(pci);
@@ -952,9 +958,7 @@ static int rockchip_pcie_rc_reset_root_port(struct pci_host_bridge *bridge,
goto deinit_clk;
}
- /* unmask hot reset/link-down reset */
- val = FIELD_PREP_WM16(PCIE_LINK_REQ_RST_NOT_INT, 0);
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
+ rockchip_pcie_unmask_dll_interrupts(rockchip, false);
ret = dw_pcie_start_link(pci);
if (ret)
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 7/9] PCI: dw-rockchip: Add pme_turn_off support
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (5 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 6/9] PCI: dw-rockchip: Add helper function for DLL interrupts Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 8/9] PCI: dw-rockchip: Set broken L1SS resume flag Sebastian Reichel
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
Prepare Rockchip PCIe controller for system suspend support by
adding the PME turn off operation.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 47 +++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index b4f53ce86079..d8968743732c 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -47,6 +47,10 @@
#define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1)
#define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0)
+/* Interrupt Status Register for Received Messages */
+#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04
+#define PME_TO_ACK BIT(9)
+
/* Interrupt Status Register Related to Legacy Interrupt */
#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
@@ -71,6 +75,11 @@
#define PCIE_CLKREQ_READY FIELD_PREP_WM16(BIT(0), 1)
#define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0)
#define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1)
+#define PME_READY_ENTER_L23 BIT(3)
+
+/* Message Request Register */
+#define PCIE_CLIENT_MSG_GEN 0x34
+#define PME_TURN_OFF FIELD_PREP_WM16(BIT(4), 1)
/* RASDES TBA information */
#define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154
@@ -439,8 +448,46 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
return 0;
}
+static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
+ struct device *dev = rockchip->pci.dev;
+ u32 status;
+ int ret;
+
+ /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */
+ rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN);
+ ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN,
+ status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10,
+ PCIE_PME_TO_L2_TIMEOUT_US);
+ if (ret) {
+ dev_warn(dev, "Failed to send PME_Turn_Off\n");
+ return;
+ }
+
+ /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */
+ ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX,
+ status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10,
+ PCIE_PME_TO_L2_TIMEOUT_US);
+ if (ret) {
+ dev_warn(dev, "Failed to receive PME_TO_Ack\n");
+ return;
+ }
+
+ /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */
+ rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX);
+ ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON,
+ status, status & PME_READY_ENTER_L23,
+ PCIE_PME_TO_L2_TIMEOUT_US / 10,
+ PCIE_PME_TO_L2_TIMEOUT_US);
+ if (ret)
+ dev_err(dev, "Failed to get ready to enter L23 message\n");
+}
+
static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
.init = rockchip_pcie_host_init,
+ .pme_turn_off = rockchip_pcie_pme_turn_off,
};
/*
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 8/9] PCI: dw-rockchip: Set broken L1SS resume flag
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (6 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 7/9] PCI: dw-rockchip: Add pme_turn_off support Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-05 13:33 ` [PATCH v9 9/9] PCI: dw-rockchip: Add system PM support Sebastian Reichel
2026-11-06 0:35 ` [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Shawn Lin
9 siblings, 0 replies; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
During system suspend, the Rockchip RC driver effectively powers off the
controller. If the link is in L1SS and the endpoint asserts CLKREQ# to
exit L1SS, the time required to wake the system and restore the
PHY/REFCLK may exceed the L1SS exit timing (L10_REFCLK_ON +
T_COMMONMODE), resulting in Link Down (LDn) and a reset of the endpoint.
Set broken_l1ss_resume flag to indicate this limitation to the PCIe
framework. This results in pci_suspend_retains_context() returning false
and PCIe client can avoid relying on device state being preserved
during system suspend.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index d8968743732c..a603475d4450 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -448,6 +448,11 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
return 0;
}
+static void rockchip_pcie_host_post_init(struct dw_pcie_rp *pp)
+{
+ pp->bridge->broken_l1ss_resume = true;
+}
+
static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -487,6 +492,7 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp)
static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
.init = rockchip_pcie_host_init,
+ .post_init = rockchip_pcie_host_post_init,
.pme_turn_off = rockchip_pcie_pme_turn_off,
};
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 9/9] PCI: dw-rockchip: Add system PM support
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (7 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 8/9] PCI: dw-rockchip: Set broken L1SS resume flag Sebastian Reichel
@ 2026-11-05 13:33 ` Sebastian Reichel
2026-11-06 0:35 ` [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Shawn Lin
9 siblings, 0 replies; 14+ messages in thread
From: Sebastian Reichel @ 2026-11-05 13:33 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Shawn Lin, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: Alexey Charkov, linux-pci, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Sebastian Reichel
Add system PM support for Rockchip PCIe Designware Controllers.
I've tested this on the Rockchip RK3576 EVB1, the Radxa ROCK 4D
and the ArmSom Sige5 boards.
While I haven't experienced any issues, most of my tests have been done
without any devices attached (i.e. default board without any extras), so
there _might_ still be some problems. As system suspend does not work at
all right now, I think it makes sense to get at least the basic
configurations working as soon as possible as it will allow us to catch
regressions by enabling system suspend in CI systems like KernelCI.
Co-developed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 102 ++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index a603475d4450..39faefaf568d 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -124,6 +124,7 @@ struct rockchip_pcie {
struct gpio_desc *rst_gpio;
struct regulator *vpcie3v3;
struct irq_domain *irq_domain;
+ u32 intx;
const struct rockchip_pcie_of_data *data;
bool supports_clkreq;
struct delayed_work trace_work;
@@ -807,6 +808,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev,
pp = &rockchip->pci.pp;
pp->ops = &rockchip_pcie_host_ops;
+ pp->suspend_poweroff = true;
ret = dw_pcie_host_init(pp);
if (ret) {
@@ -1030,6 +1032,100 @@ static int rockchip_pcie_rc_reset_root_port(struct pci_host_bridge *bridge,
return ret;
}
+static int rockchip_pcie_suspend(struct device *dev)
+{
+ struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
+ struct dw_pcie *pci = &rockchip->pci;
+ int ret;
+
+ if (rockchip->data->mode == DW_PCIE_EP_TYPE)
+ return 0;
+
+ if (pci->suspended)
+ return 0;
+
+ ret = dw_pcie_suspend_noirq(pci);
+ if (ret)
+ return ret;
+
+ rockchip->intx = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MASK_LEGACY);
+ rockchip->intx &= PCIE_INTR_MASK;
+
+ gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
+ rockchip_pcie_phy_deinit(rockchip);
+ clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
+ reset_control_assert(rockchip->rst);
+ if (rockchip->vpcie3v3)
+ regulator_disable(rockchip->vpcie3v3);
+
+ return 0;
+}
+
+static int rockchip_pcie_resume(struct device *dev)
+{
+ struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
+ struct dw_pcie *pci = &rockchip->pci;
+ int ret;
+
+ if (rockchip->data->mode == DW_PCIE_EP_TYPE)
+ return 0;
+
+ if (rockchip->vpcie3v3) {
+ ret = regulator_enable(rockchip->vpcie3v3);
+ if (ret) {
+ dev_err(dev, "regulator enable failed: %d\n", ret);
+ return ret;
+ }
+ }
+
+ ret = rockchip_pcie_phy_init(rockchip);
+ if (ret) {
+ dev_err(dev, "phy init failed: %d\n", ret);
+ goto err_disable_regulator;
+ }
+
+ ret = reset_control_deassert(rockchip->rst);
+ if (ret) {
+ dev_err(dev, "reset deassert failed: %d\n", ret);
+ goto err_deinit_phy;
+ }
+
+ ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);
+ if (ret) {
+ dev_err(dev, "clock init failed: %d\n", ret);
+ goto err_assert_reset;
+ }
+
+ rockchip_pcie_writel_apb(rockchip, FIELD_PREP_WM16(PCIE_INTR_MASK, rockchip->intx),
+ PCIE_CLIENT_INTR_MASK_LEGACY);
+
+ rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, 0);
+ rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_RC);
+
+ ret = dw_pcie_resume_noirq(pci);
+ if (ret) {
+ dev_err(dev, "failed to resume: %d\n", ret);
+ goto err_reassert_rst;
+ }
+
+ rockchip_pcie_unmask_dll_interrupts(rockchip, false);
+
+ return 0;
+
+err_reassert_rst:
+ gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
+ clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
+err_assert_reset:
+ reset_control_assert(rockchip->rst);
+err_deinit_phy:
+ rockchip_pcie_phy_deinit(rockchip);
+err_disable_regulator:
+ if (rockchip->vpcie3v3)
+ regulator_disable(rockchip->vpcie3v3);
+
+ return ret;
+}
+
static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
.mode = DW_PCIE_RC_TYPE,
};
@@ -1060,11 +1156,17 @@ static const struct of_device_id rockchip_pcie_of_match[] = {
{},
};
+static const struct dev_pm_ops rockchip_pcie_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend,
+ rockchip_pcie_resume)
+};
+
static struct platform_driver rockchip_pcie_driver = {
.driver = {
.name = "rockchip-dw-pcie",
.of_match_table = rockchip_pcie_of_match,
.suppress_bind_attrs = true,
+ .pm = &rockchip_pcie_pm_ops,
},
.probe = rockchip_pcie_probe,
};
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support
2026-11-05 13:33 [PATCH v9 0/9] PCI: dw-rockchip: add system suspend support Sebastian Reichel
` (8 preceding siblings ...)
2026-11-05 13:33 ` [PATCH v9 9/9] PCI: dw-rockchip: Add system PM support Sebastian Reichel
@ 2026-11-06 0:35 ` Shawn Lin
9 siblings, 0 replies; 14+ messages in thread
From: Shawn Lin @ 2026-11-06 0:35 UTC (permalink / raw)
To: Sebastian Reichel, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Philipp Zabel, Jingoo Han, Liam Girdwood, Mark Brown,
Yury Norov (NVIDIA), Nicolas Frattaroli
Cc: shawn.lin, Alexey Charkov, linux-pci, linux-arm-kernel,
linux-rockchip, linux-kernel, kernel
Hi Sebasitain,
在 2026/11/05 星期四 21:33, Sebastian Reichel 写道:
> I've been working on fixing up at least basic system suspend support on
> the Rockchip RK3576 platform. This series is a follow-up for Shawn Lin's
> series with feedback from Niklas Cassel and Manivannan Sadhasivam being
> handled as well as some of my own changes fixing up things I noticed.
>
> Tested boards:
> * Sige5 (RK3576)
> * Rock 4D (RK3576)
> * RK3588 EVB1 (RK3588)
> * ODROID-M1 (RK3568), Igor Velkov (previous version)
>
> Somewhat related, RK3588 also needs [0] to fix PCIe IOMMU issues after
> resume. Additionally RK3588 runs into SError on resume due to a USB2 PHY
> problem, which is fixed via [1]. RK3576 does not use PCIe IOMMU and does
> not run into the USB2 PHY problem (at least Sige5 and Rock 4D), so this
> series can easily be tested standalone on that platform.
>
> [0] https://lore.kernel.org/all/20260929034510.2023173-1-praan@google.com/
> [1] https://lore.kernel.org/linux-phy/20261105-phy-rockchip-inno-usb2-clock-fix-v3-0-b20608c08b94@collabora.com/
>
> Changes in v9:
> - Link to v8: https://patch.msgid.link/20261105-rockchip-pcie-system-suspend-v8-0-0434b4f373bc@collabora.com
> - Collect Reviewed-by tag from Shawn Lin for pme_turn_off patch
> - Ignore suggestion from Shawn Lin to make pme_turn_off return error
> codes as out-of-scope. I think it is sensible, but should be done
> in a separate series as it will touch all glue drivers. (Shawn Lin)
> - Update rockchip_pcie_rc_reset_root_port() to also use the
> rockchip_pcie_set_controller_mode() helper (Sashiko)
> - Update DLL IRQ unmask helper to also handle instances not involving
> PCIE_RDLH_LINK_UP_CHGED (Sashiko)
> - Move INTx caching after dw_pcie_suspend_noirq() to avoid a race
> condition (Sashiko)
>
You seem to forget to take TB tag from Igor Velkov as he tested your v8.
> Changes in v8:
> - Link to v7: https://patch.msgid.link/20261104-rockchip-pcie-system-suspend-v7-0-6ae6875939a2@collabora.com
> - Drop the final debug patch; I took that over from Rockchip's vendor
> tree as it seems useful for debug purposes. Using it involves reading
> the register via /dev/mem. It's not directly tied to actual system PM
> support itself, so it can be submitted separetely. It's not worth
> fighting Sashiko for it.
> - In LTSSM control mode patch also replace one occurance that I missed
> - In system PM support patch add guard not suspending an already
> suspended PCIe devices, which can happen when resume failed following
> the example of UltraRISC (Sashiko)
> - In the same patch replace 0xffff mask with PCIE_INTR_MASK to avoid
> overflow issue; the new mask is not functional equivalent as we just
> work on the lower 8 bit now. The following 8 bit are reserved on
> RK3588 and RK3576 anyways, though. Thus this effectivly better
> documents the purpose of the cached value. (Sashiko)
> - Drop incorrect custom PERST# handling in the resume handler (Sashiko)
> - Modify interrupt masking to follow RC instead of EP logic (Sashiko)
> - I've not picked up the Tested-by tag from Igor Velkov on v7
> as there are some changes (even though I'm fairly sure they
> don't matter), which add RK3568 to the tested SoC range.
>
> Changes in v7:
> * Link to v6: https://patch.msgid.link/20260908-rockchip-pcie-system-suspend-v6-0-fbabcca9921b@collabora.com
> * Rebased to v7.4-rc1
> * Collect Reviewed-by tags from Shawn Lin to (mostly) unchanged patches;
> I skipped some due to changes in v7
> * Keep dev_err_probe() message for rockchip_pcie_phy_init in patch
> restoring vpcie3v3 regulator handling
> * Avoid dynamic mask for extra flags in "enhanced LTSSM control mode helper"
> by just adding specific support for the extra flag needed. Apparently
> some compiler configurations don't like it.
> * Avoid duplicated register define in In pme_turn_off patch
> * Move bit defines to the correct register defines in pme_turn_off patch
> * In broken L1SS resume flag patch move the explanation comment from the
> code to the commit message (FWIW this comment is not AI generated by
> me, but was copied from the Qcom implementation).
> * In system PM support patch, set pp->suspend_poweroff to fix the issue
> identified by Igor
> * In system PM support patch, just return 0 for DW_PCIE_EP_TYPE (Mani)
> to keep the status-quo (I've not tested this specifically).
> * In system PM support patch, use the same init order as probe (Sashiko)
> * In clear debug buffer patch, drop dw_pcie_dbi_ro_wr_dis(), which
> is already done by the core nowadays (Sashiko, Mani)
> * In clear debug buffer patch, fix actual register write (Sashiko)
> * In clear debug buffer patch, update patch description with
> better explanation about the register (Mani)
>
> Changes in v6:
> * https://lore.kernel.org/r/20260316-rockchip-pcie-system-suspend-v5-0-5bb5ad37d643@collabora.com
> * Rebase to pci/next
> * Minor changes to make checkpatch happy
> * Update patch description of the last patch and drop RFC tag
> according to feedback from Shawn Lin
> * Prepend new patch, which fixes Nicolas Frattaroli's conversion
> to FIELD_PREP_WM16 accidently dropping a flag.
> * Add another new patch, which sets .broken_l1ss_resume to tell the
> PCI core that the controller is powered off during suspend following
> the Qcom example
>
> Changes in v5:
> * https://lore.kernel.org/r/20251029-rockchip-pcie-system-suspend-v4-0-ce2e1b0692d2@collabora.com
> * rebase to v7.0-rc1
> * Add an RFC patch at the end with some bits I found in the Rockchip vendor kernel;
> * Made some tests on Rock 5B+ (RK3588); with this patch series suspending works
> when setting pm_test to devices. A full system suspend fails in a later step,
> but that is independent of PCIe.
>
> Changes in v4:
> * https://lore.kernel.org/linux-pci/1744940759-23823-1-git-send-email-shawn.lin@rock-chips.com/
> * rename rockchip_pcie_get_ltssm to rockchip_pcie_get_ltssm_status_reg
> in a separate patch (Niklas Cassel)
> * rename rockchip_pcie_get_pure_ltssm to rockchip_pcie_get_ltssm_state
> in a separate patch (Niklas Cassel)
> * Move devm_phy_get out of phy_init to probe in a separate patch
> (Manivannan Sadhasivam)
> * Add helper function for enhanced LTSSM control mode in a separate patch
> (Niklas Cassel)
> * Add helper function for controller mode in a separate patch
> (Niklas Cassel)
> * Add helper function for DDL indicator in a separate patch
> (Niklas Cassel)
> * Move rockchip_pcie_pme_turn_off implementation in a separate patch
> * Rebase to v6.18-rc3 using new FIELD_PREP_WM16()
> * Improve readability of PME_TURN_OFF/PME_TO_ACK defines (Manivannan Sadhasivam)
> * Fix usage of reverse Xmas (Manivannan Sadhasivam)
> * Assert PERST# before turning off other resources (Manivannan Sadhasivam)
> * Improve some error messages (Manivannan Sadhasivam)
> * Rename goto labels as per their purpose (Manivannan Sadhasivam)
> * Add extra patch for dw_pcie_resume_noirq, since I've seen errors
> during resume on boards not having anything plugged into their PCIe
> port
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> Sebastian Reichel (9):
> PCI: dw-rockchip: Fix LTSSM set functions
> PCI: dw-rockchip: Restore vpcie3v3 regulator handle
> PCI: dw-rockchip: Move devm_phy_get out of phy_init
> PCI: dw-rockchip: Add helper function for enhanced LTSSM control mode
> PCI: dw-rockchip: Add helper function for controller mode
> PCI: dw-rockchip: Add helper function for DLL interrupts
> PCI: dw-rockchip: Add pme_turn_off support
> PCI: dw-rockchip: Set broken L1SS resume flag
> PCI: dw-rockchip: Add system PM support
>
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 283 +++++++++++++++++++++-----
> 1 file changed, 228 insertions(+), 55 deletions(-)
> ---
> base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
> change-id: 20251028-rockchip-pcie-system-suspend-86cf08a7b229
>
> Best regards,
> --
> Sebastian Reichel <sebastian.reichel@collabora.com>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread