From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v17 09/19] cxl: Refresh cached PCI HDM decoder settings
Date: Thu, 05 Nov 2026 19:17:36 +0000 [thread overview]
Message-ID: <sashiko-outbox-199836@kernel.org> (raw)
In-Reply-To: <20261105185917.2667656-10-smadhavan@nvidia.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] cxl: split declaration and init of __free() variable in cxl_hdm_refresh_decoder()
- [Low] cxl: unused struct cxl_hdm_info forward declaration in include/cxl/cxl.h
--
commit 0273d4d08ae78949f901788b93c7db64fb203e17
Author: Srirangan Madhavan <smadhavan@nvidia.com>
cxl: Refresh cached PCI HDM decoder settings
This commit refreshes the cached PCI HDM decoder state when hardware HDM
decoders are enumerated, committed, or reset, and validates the enumerated
decoder count against the cached count.
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 85f9abf58a42b..ec387070d7adb 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -725,6 +725,24 @@ static void cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt)
> *tgt |= FIELD_PREP(GENMASK_ULL(63, 56), t[7]->port_id);
> }
>
> +static void cxl_hdm_refresh_decoder(struct cxl_hdm *cxlhdm,
> + struct cxl_decoder *cxld)
> +{
> + void __iomem *hdm = cxlhdm->regs.hdm_decoder;
> + struct pci_dev *pdev __free(pci_dev_put) = NULL;
> +
> + if (!hdm)
> + return;
> + if (!is_endpoint_decoder(&cxld->dev))
> + return;
> +
> + pdev = cxl_port_get_uport_pci_dev(cxlhdm->port);
[Severity: Low]
As reported by Cheatham, Benjamin on v13 [1], this isn't a bug, but in
cxl_hdm_refresh_decoder() in drivers/cxl/core/hdm.c, pdev is declared with
__free(pci_dev_put) = NULL at the top of the function and assigned later after
the !hdm and !is_endpoint_decoder(&cxld->dev) early returns.
Should pdev be defined and initialized in a single statement where
cxl_port_get_uport_pci_dev(cxlhdm->port) is called after the early returns,
matching cxl_hdm_check_decoder_count() in drivers/cxl/core/pci.c and the
kernel Cleanup API conventions?
[ ... ]
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 6d6e564be27a9..341a7c52894ab 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -26,6 +26,7 @@ enum cxl_devtype {
> };
>
> struct cxl_region;
> +struct cxl_hdm_info;
[Severity: Low]
This isn't a bug, but struct cxl_hdm_info is not referenced anywhere in
include/cxl/cxl.h (it is defined in include/cxl/hdm.h and forward-declared in
include/linux/pci.h). Can this forward declaration be dropped from
include/cxl/cxl.h?
[1] https://lore.kernel.org/r/2c37c82b-8db6-44d1-868b-0b98bae57459@amd.com
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261105185917.2667656-1-smadhavan@nvidia.com?part=9
next prev parent reply other threads:[~2026-11-05 19:17 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 18:58 [PATCH v17 00/19] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-11-05 18:58 ` [PATCH v17 01/19] cxl: Clarify decoder interleave limit Srirangan Madhavan
2026-11-05 19:03 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 02/19] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-11-05 19:12 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 03/19] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-11-05 19:06 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 04/19] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-11-05 19:07 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 05/19] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-11-05 19:09 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 06/19] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-11-05 19:07 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 07/19] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-11-05 19:16 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 08/19] cxl: Move cxl_rwsem into built-in code Srirangan Madhavan
2026-11-05 19:09 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 09/19] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-11-05 19:17 ` sashiko-bot [this message]
2026-11-05 18:59 ` [PATCH v17 10/19] cxl: Build register block helpers into the kernel Srirangan Madhavan
2026-11-05 19:23 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 11/19] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-11-05 19:30 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 12/19] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-11-05 19:17 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 13/19] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-11-05 19:44 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 14/19] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-11-05 19:33 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 15/19] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-11-05 19:34 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 16/19] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-11-05 19:35 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 17/19] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-11-05 19:43 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 18/19] PCI/CXL: Flush host and device caches for " Srirangan Madhavan
2026-11-05 19:56 ` sashiko-bot
2026-11-05 18:59 ` [PATCH v17 19/19] cxl: Add KUnit checks for HDM decoder unpacking Srirangan Madhavan
2026-11-05 19:38 ` sashiko-bot
2026-11-05 19:31 ` [PATCH v17 00/19] PCI/CXL: Add CXL reset support for Type 2 devices Alison Schofield
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