[PATCH v2 0/7] Apple M3, M3 Pro/Max/Ultra PCIe device trees

[PATCH v2 0/7] Apple M3, M3 Pro/Max/Ultra PCIe device trees

[Janne Grunau]

Hej,

this series contains the device tree changes for PCIe support on all 
M3, M3 Pro, M3 Max and M3 Ultra devices.
The PCIe controller on these SoCs is compatible to the M2 Pro/Max one.
So add the new per SoC compatibles to the dt-bindings and add PCIe
device nodes for all M3, M3 Pro, M3 Max and M3 Ultra devices.
The series contains a fix for the M3 (t8122) power-state devices tree
nodes. A power-state required for the PCIe controller and the NVMe was
not correctly represented. MacOS keeps this power-state always on and so
does the device tree for M2 Pro/Max. Do the same on M3.

Based on apple-soc/dt-7.5 [1] to avoid trivial conflicts with the NVMe
series and to import the M3 DART dt-bindings from [2].

The series passes make dtbs_check and make dt_binding_check and does
not introduce additional dt-style-check --mode strict warnings with
dt-style-check from next-20261103

ciao,

Janne

Link: https://github.com/AsahiLinux/linux/tree/apple-soc/dt-7.5 [1]
Link: https://patch.msgid.link/20260925-apple-mtp-keyboard-final-v4-0-304c267518f4@gmail.com [2]
Signed-off-by: Janne Grunau <j@jannau.net>
---
Changes in v2:
- capitalized PCI and reordered words in dt-binding's subject line
- adjusted WiFi/Bluetooth PCI compatibles to BCM4388 for M3
  Pro/Max/Ultra devices
- Link to v1: https://patch.msgid.link/20261105-apple-m3-pcie-v1-0-e00a72a604f8@jannau.net

To: Sven Peter <sven@kernel.org>
To: Janne Grunau <j@jannau.net>
To: Neal Gompa <neal@gompa.dev>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Joshua Peisach <jpeisach@ubuntu.com>
To: Michael Reeves <michael.reeves077@gmail.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kwilczynski@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
To: Mark Kettenis <kettenis@openbsd.org>
Cc: asahi@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org

---
Alyssa Milburn (1):
      arm64: dts: apple: t8122: Add PCIe device nodes

Janne Grunau (4):
      arm64: dts: apple: t8122: Keep ps_apcie_phy_sw always-on
      dt-bindings: PCI: apple,pcie: Add M3 generation compatibles
      arm64: dts: apple: t6030: Add PCIe nodes
      arm64: dts: apple: t6032-j575d: Add PCIe device nodes

Yureka Lilian (2):
      arm64: dts: apple: t6031: Add PCIe nodes
      arm64: dts: apple: t603x-j514-j516: Add PCIe device nodes

 .../devicetree/bindings/pci/apple,pcie.yaml        |   6 +
 arch/arm64/boot/dts/apple/t6030-j514s.dts          |   8 +
 arch/arm64/boot/dts/apple/t6030-j516s.dts          |   8 +
 arch/arm64/boot/dts/apple/t6030.dtsi               | 165 +++++++++++++++++++
 arch/arm64/boot/dts/apple/t6031-die0.dtsi          | 157 ++++++++++++++++++
 arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi     |   9 ++
 arch/arm64/boot/dts/apple/t6031-j514c.dts          |   8 +
 arch/arm64/boot/dts/apple/t6031-j516c.dts          |   8 +
 arch/arm64/boot/dts/apple/t6031.dtsi               |   1 +
 arch/arm64/boot/dts/apple/t6032-j575d.dts          |  72 +++++++++
 arch/arm64/boot/dts/apple/t6034-j514m.dts          |   8 +
 arch/arm64/boot/dts/apple/t6034-j516m.dts          |   8 +
 arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi     |  41 +++++
 arch/arm64/boot/dts/apple/t8122-j433.dts           |  28 ++++
 arch/arm64/boot/dts/apple/t8122-j434.dts           |  38 +++++
 arch/arm64/boot/dts/apple/t8122-j504.dts           |  26 +++
 arch/arm64/boot/dts/apple/t8122-j613.dts           |   8 +
 arch/arm64/boot/dts/apple/t8122-j615.dts           |   8 +
 arch/arm64/boot/dts/apple/t8122-jxxx.dtsi          |  29 +++-
 arch/arm64/boot/dts/apple/t8122-pmgr.dtsi          |   2 +-
 arch/arm64/boot/dts/apple/t8122.dtsi               | 175 +++++++++++++++++++++
 21 files changed, 811 insertions(+), 2 deletions(-)
---
base-commit: 6c799b8c0df41869fa0d059f7e54f8f84b3989ee
change-id: 20261104-apple-m3-pcie-ae72b846baaf

Best regards,
--  
Janne Grunau <j@jannau.net>

[PATCH v2 1/7] arm64: dts: apple: t8122: Keep ps_apcie_phy_sw always-on

[Janne Grunau]

The APCIE_PHY_SW power state is in Apple's device tree a child of the
virtual storage and general purpose PCIe power-states. MacOS however
keeps it always powered on. Mirror this behaviour like the M2 Pro/Max
device trees already do in t602x-pgmr.dtsi.

Fixes: c65ab4905e58 ("arm64: dts: apple: Initial t8122 (M3) device trees")
Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t8122-pmgr.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi
index 3f8be74b5ea8..3206787dd208 100644
--- a/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi
+++ b/arch/arm64/boot/dts/apple/t8122-pmgr.dtsi
@@ -899,7 +899,7 @@ ps_apcie_phy_sw: power-controller@4a0 {
 		#power-domain-cells = <0>;
 		#reset-cells = <0>;
 		label = "apcie_phy_sw";
-		power-domains = <&ps_apcie_st>, <&ps_apcie_gp>;
+		apple,always-on; /* macOS does not turn this off */
 	};
 
 	ps_atc0_cio_pcie: power-controller@4a8 {

-- 
2.56.0

[PATCH v2 2/7] dt-bindings: PCI: apple,pcie: Add M3 generation compatibles

[Janne Grunau]

The PCIe controller on Apple M3, M3 Pro, Max and Ultra SoCs are
compatible with the one on M2 Pro and Max. Add their per SoC compatibles
"apple,t8122-pcie" (M3), "apple,t6030-pcie" (M3 Pro) and
"apple,t6031-pcie" (M3 Max/Ultra) to the bindings.

Signed-off-by: Janne Grunau <j@jannau.net>

---
Changes in v2:
- modified subject line
---
 Documentation/devicetree/bindings/pci/apple,pcie.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml
index c0852be04f6d..a40b5d5b9a5b 100644
--- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml
@@ -41,6 +41,12 @@ properties:
               - apple,t8112-pcie
               - apple,t6000-pcie
           - const: apple,pcie
+      - items:
+          - enum:
+              - apple,t6030-pcie
+              - apple,t6031-pcie
+              - apple,t8122-pcie
+          - const: apple,t6020-pcie
       - const: apple,t6020-pcie
 
   reg:

-- 
2.56.0

[PATCH v2 3/7] arm64: dts: apple: t6030: Add PCIe nodes

[Janne Grunau]

Add the PCIe controller, its ports, IOMMUs and clock request pins to the
base M3 Pro .dtsi file.
M3 Pro is only used in 14 and 16-inch Macbook Pro which connect PCIe
devices to the port 0 and 1.

Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t6030.dtsi | 165 +++++++++++++++++++++++++++++++++++
 1 file changed, 165 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6030.dtsi b/arch/arm64/boot/dts/apple/t6030.dtsi
index 85a16d03e22f..4bac0fbcea8c 100644
--- a/arch/arm64/boot/dts/apple/t6030.dtsi
+++ b/arch/arm64/boot/dts/apple/t6030.dtsi
@@ -7,6 +7,7 @@
  * Copyright The Asahi Linux Contributors
  */
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/apple-aic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/apple.h>
@@ -431,6 +432,14 @@ i2c8_pins: i2c8-pins {
 				pinmux = <APPLE_PINMUX(51, 1)>,
 					 <APPLE_PINMUX(50, 1)>;
 			};
+
+			pcie_pins: pcie-pins {
+				// clkreq pins
+				pinmux = <APPLE_PINMUX(163, 1)>,
+					 <APPLE_PINMUX(164, 1)>,
+					 <APPLE_PINMUX(165, 1)>,
+					 <APPLE_PINMUX(166, 1)>;
+			};
 		};
 
 		pmgr: power-management@350700000 {
@@ -579,6 +588,162 @@ nvme: nvme@38dcc0000 {
 
 			apple,sart = <&sart>;
 		};
+
+		pcie0: pcie@580000000 {
+			device_type = "pci";
+			compatible = "apple,t6030-pcie", "apple,t6020-pcie";
+
+			reg = <0x5 0x80000000 0x0 0x1000000>,	/* config */
+			      <0x5 0x91000000 0x0 0x4000>,	/* rc */
+			      <0x5 0x94008000 0x0 0x4000>,	/* port0 */
+			      <0x5 0x95008000 0x0 0x4000>,	/* port1 */
+			      <0x5 0x96008000 0x0 0x4000>,	/* port2 */
+			      <0x5 0x97008000 0x0 0x4000>,	/* port3 */
+			      <0x5 0x9e020000 0x0 0x4000>,	/* phy0 */
+			      <0x5 0x9e024000 0x0 0x4000>,	/* phy1 */
+			      <0x5 0x9e028000 0x0 0x4000>,	/* phy2 */
+			      <0x5 0x9e02c000 0x0 0x4000>;	/* phy3 */
+			reg-names = "config", "rc",
+				    "port0", "port1", "port2", "port3",
+				    "phy0", "phy1", "phy2", "phy3";
+			ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
+				 <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;
+			#address-cells = <3>;
+			bus-range = <0 4>;
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1038 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 1047 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 1056 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 1065 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommu-map = <0x100 &pcie0_dart_0 1 1>,
+				    <0x200 &pcie0_dart_1 1 1>,
+				    <0x300 &pcie0_dart_2 1 1>,
+				    <0x400 &pcie0_dart_3 1 1>;
+			iommu-map-mask = <0xff00>;
+
+			msi-controller;
+			msi-parent = <&pcie0>;
+			msi-ranges = <&aic AIC_IRQ 1342 IRQ_TYPE_EDGE_RISING 32>;
+
+			pinctrl-0 = <&pcie_pins>;
+			pinctrl-names = "default";
+			power-domains = <&ps_apcie_sys_gp>;
+			#size-cells = <2>;
+
+			port00: pci@0,0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
+						<0 0 0 2 &port00 0 0 0 1>,
+						<0 0 0 3 &port00 0 0 0 2>,
+						<0 0 0 4 &port00 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+				reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+			};
+
+			port01: pci@1,0 {
+				device_type = "pci";
+				reg = <0x800 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
+						<0 0 0 2 &port01 0 0 0 1>,
+						<0 0 0 3 &port01 0 0 0 2>,
+						<0 0 0 4 &port01 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+				reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+			};
+
+			port02: pci@2,0 {
+				device_type = "pci";
+				reg = <0x1000 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
+						<0 0 0 2 &port02 0 0 0 1>,
+						<0 0 0 3 &port02 0 0 0 2>,
+						<0 0 0 4 &port02 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+				reset-gpios = <&pinctrl_ap 169 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+
+				status = "disabled";
+			};
+
+			port03: pci@3,0 {
+				device_type = "pci";
+				reg = <0x1800 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
+						<0 0 0 2 &port03 0 0 0 1>,
+						<0 0 0 3 &port03 0 0 0 2>,
+						<0 0 0 4 &port03 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+				reset-gpios = <&pinctrl_ap 170 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+
+				status = "disabled";
+			};
+		};
+
+		pcie0_dart_0: iommu@594000000 {
+			compatible = "apple,t6030-dart", "apple,t8110-dart";
+			reg = <0x5 0x94000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1039 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_sys_gp>;
+		};
+
+		pcie0_dart_1: iommu@595000000 {
+			compatible = "apple,t6030-dart", "apple,t8110-dart";
+			reg = <0x5 0x95000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1048 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_sys_gp>;
+		};
+
+		pcie0_dart_2: iommu@596000000 {
+			compatible = "apple,t6030-dart", "apple,t8110-dart";
+			reg = <0x5 0x96000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1057 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_sys_gp>;
+
+			status = "disabled";
+		};
+
+		pcie0_dart_3: iommu@597000000 {
+			compatible = "apple,t6030-dart", "apple,t8110-dart";
+			reg = <0x5 0x97000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 1066 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_sys_gp>;
+
+			status = "disabled";
+		};
 	};
 
 	timer {

-- 
2.56.0

[PATCH v2 4/7] arm64: dts: apple: t6031: Add PCIe nodes

[Janne Grunau]

From: Yureka Lilian <yureka@cyberchaos.dev>

Add the PCIe controller, its ports, IOMMUs and clock request pins to the
die0 M3 Max/Ultra .dtsi file.
All M3 Max and Ultra devices use port 0 and 1 so enable them and their
IOMMU.

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
Co-developed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t6031-die0.dtsi      | 157 +++++++++++++++++++++++++
 arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi |   9 ++
 arch/arm64/boot/dts/apple/t6031.dtsi           |   1 +
 3 files changed, 167 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6031-die0.dtsi b/arch/arm64/boot/dts/apple/t6031-die0.dtsi
index b14443436e26..434b16b2a6bf 100644
--- a/arch/arm64/boot/dts/apple/t6031-die0.dtsi
+++ b/arch/arm64/boot/dts/apple/t6031-die0.dtsi
@@ -207,4 +207,161 @@ serial0: serial@391200000 {
 
 		status = "disabled";
 	};
+
+	pcie0: pcie@580000000 {
+		device_type = "pci";
+		compatible = "apple,t6031-pcie", "apple,t6020-pcie";
+
+		reg = <0x5 0x80000000 0x0 0x1000000>,	/* config */
+		      <0x5 0x91000000 0x0 0x4000>,	/* rc */
+		      <0x5 0x94008000 0x0 0x4000>,	/* port0 */
+		      <0x5 0x95008000 0x0 0x4000>,	/* port1 */
+		      <0x5 0x96008000 0x0 0x4000>,	/* port2 */
+		      <0x5 0x97008000 0x0 0x4000>,	/* port3 */
+		      <0x5 0x9e020000 0x0 0x4000>,	/* phy0 */
+		      <0x5 0x9e024000 0x0 0x4000>,	/* phy1 */
+		      <0x5 0x9e028000 0x0 0x4000>,	/* phy2 */
+		      <0x5 0x9e02c000 0x0 0x4000>;	/* phy3 */
+		reg-names = "config", "rc",
+			    "port0", "port1", "port2", "port3",
+			    "phy0", "phy1", "phy2", "phy3";
+
+		ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
+			 <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;
+		#address-cells = <3>;
+		bus-range = <0 4>;
+
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_IRQ 0 1491 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ 0 1500 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ 0 1509 IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_IRQ 0 1518 IRQ_TYPE_LEVEL_HIGH>;
+
+		iommu-map = <0x100 &pcie0_dart_0 1 1>,
+			    <0x200 &pcie0_dart_1 1 1>,
+			    <0x300 &pcie0_dart_2 1 1>,
+			    <0x400 &pcie0_dart_3 1 1>;
+		iommu-map-mask = <0xff00>;
+
+		msi-controller;
+		msi-parent = <&pcie0>;
+		msi-ranges = <&aic AIC_IRQ 0 1854 IRQ_TYPE_EDGE_RISING 32>;
+
+		pinctrl-0 = <&pcie_pins>;
+		pinctrl-names = "default";
+		power-domains = <&ps_apcie_sys_gp>;
+		#size-cells = <2>;
+
+		port00: pci@0,0 {
+			device_type = "pci";
+			reg = <0x0 0x0 0x0 0x0 0x0>;
+			ranges;
+			#address-cells = <3>;
+
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
+					<0 0 0 2 &port00 0 0 0 1>,
+					<0 0 0 3 &port00 0 0 0 2>,
+					<0 0 0 4 &port00 0 0 0 3>;
+			interrupt-map-mask = <0 0 0 7>;
+			reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;
+			#size-cells = <2>;
+		};
+
+		port01: pci@1,0 {
+			device_type = "pci";
+			reg = <0x800 0x0 0x0 0x0 0x0>;
+			ranges;
+			#address-cells = <3>;
+
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
+					<0 0 0 2 &port01 0 0 0 1>,
+					<0 0 0 3 &port01 0 0 0 2>,
+					<0 0 0 4 &port01 0 0 0 3>;
+			interrupt-map-mask = <0 0 0 7>;
+			reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;
+			#size-cells = <2>;
+		};
+
+		port02: pci@2,0 {
+			device_type = "pci";
+			reg = <0x1000 0x0 0x0 0x0 0x0>;
+			ranges;
+			#address-cells = <3>;
+
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
+					<0 0 0 2 &port02 0 0 0 1>,
+					<0 0 0 3 &port02 0 0 0 2>,
+					<0 0 0 4 &port02 0 0 0 3>;
+			interrupt-map-mask = <0 0 0 7>;
+			reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;
+			#size-cells = <2>;
+
+			status = "disabled";
+		};
+
+		port03: pci@3,0 {
+			device_type = "pci";
+			reg = <0x1800 0x0 0x0 0x0 0x0>;
+			ranges;
+			#address-cells = <3>;
+
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
+					<0 0 0 2 &port03 0 0 0 1>,
+					<0 0 0 3 &port03 0 0 0 2>,
+					<0 0 0 4 &port03 0 0 0 3>;
+			interrupt-map-mask = <0 0 0 7>;
+			reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;
+			#size-cells = <2>;
+
+			status = "disabled";
+		};
+	};
+
+	pcie0_dart_0: iommu@594000000 {
+		compatible = "apple,t6031-dart", "apple,t8110-dart";
+		reg = <0x5 0x94000000 0x0 0x4000>;
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_IRQ 0 1492 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		power-domains = <&ps_apcie_sys_gp>;
+	};
+
+	pcie0_dart_1: iommu@595000000 {
+		compatible = "apple,t6031-dart", "apple,t8110-dart";
+		reg = <0x5 0x95000000 0x0 0x4000>;
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_IRQ 0 1501 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		power-domains = <&ps_apcie_sys_gp>;
+	};
+
+	pcie0_dart_2: iommu@596000000 {
+		compatible = "apple,t6031-dart", "apple,t8110-dart";
+		reg = <0x5 0x96000000 0x0 0x4000>;
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_IRQ 0 1510 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		power-domains = <&ps_apcie_sys_gp>;
+
+		status = "disabled";
+	};
+
+	pcie0_dart_3: iommu@597000000 {
+		compatible = "apple,t6031-dart", "apple,t8110-dart";
+		reg = <0x5 0x97000000 0x0 0x4000>;
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_IRQ 0 1519 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		power-domains = <&ps_apcie_sys_gp>;
+
+		status = "disabled";
+	};
 };
diff --git a/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi
index 0c0d09964e69..1c29d0ef8a67 100644
--- a/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi
+++ b/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi
@@ -5,6 +5,8 @@
  * Copyright The Asahi Linux Contributors
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 &pinctrl_ap {
 	i2c0_pins: i2c0-pins {
 		pinmux = <APPLE_PINMUX(56, 1)>,
@@ -50,4 +52,11 @@ i2c8_pins: i2c8-pins {
 		pinmux = <APPLE_PINMUX(72, 1)>,
 			 <APPLE_PINMUX(73, 1)>;
 	};
+
+	pcie_pins: pcie-pins {
+		pinmux = <APPLE_PINMUX(0, 1)>,
+			 <APPLE_PINMUX(1, 1)>,
+			 <APPLE_PINMUX(2, 1)>,
+			 <APPLE_PINMUX(3, 1)>;
+	};
 };
diff --git a/arch/arm64/boot/dts/apple/t6031.dtsi b/arch/arm64/boot/dts/apple/t6031.dtsi
index 30a91c1a47d2..9fd1d0f46fc3 100644
--- a/arch/arm64/boot/dts/apple/t6031.dtsi
+++ b/arch/arm64/boot/dts/apple/t6031.dtsi
@@ -5,6 +5,7 @@
  * Copyright The Asahi Linux Contributors
  */
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/apple-aic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/apple.h>

-- 
2.56.0

[PATCH v2 5/7] arm64: dts: apple: t8122: Add PCIe device nodes

[Janne Grunau]

From: Alyssa Milburn <amilburn@zall.org>

Add the PCIe controller, its ports, IOMMUs and clock request pins to the
base M3 Pro .dtsi file.

Add PCIe devices for WiFi, Bluetooth, Ethernet, SD-Card reader and USB
xHCI to device trees and enable their ports and IOMMU if necessary.
The bootloader will fill MAC addresses and calibration data properties
in their device nodes.

Signed-off-by: Alyssa Milburn <amilburn@zall.org>
Co-developed-by: Michael Reeves <michael.reeves077@gmail.com>
Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
Signed-off-by: Janne Grunau <j@jannau.net>
---
 arch/arm64/boot/dts/apple/t8122-j433.dts  |  28 +++++
 arch/arm64/boot/dts/apple/t8122-j434.dts  |  38 +++++++
 arch/arm64/boot/dts/apple/t8122-j504.dts  |  26 +++++
 arch/arm64/boot/dts/apple/t8122-j613.dts  |   8 ++
 arch/arm64/boot/dts/apple/t8122-j615.dts  |   8 ++
 arch/arm64/boot/dts/apple/t8122-jxxx.dtsi |  29 ++++-
 arch/arm64/boot/dts/apple/t8122.dtsi      | 175 ++++++++++++++++++++++++++++++
 7 files changed, 311 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/apple/t8122-j433.dts b/arch/arm64/boot/dts/apple/t8122-j433.dts
index 34205d173a9b..6c9185dc01b8 100644
--- a/arch/arm64/boot/dts/apple/t8122-j433.dts
+++ b/arch/arm64/boot/dts/apple/t8122-j433.dts
@@ -16,4 +16,32 @@
 / {
 	compatible = "apple,j433", "apple,t8122", "apple,arm-platform";
 	model = "Apple iMac (24-inch, 2x USB-C, M3, 2023)";
+
+	aliases {
+		ethernet0 = &ethernet0;
+	};
+};
+
+&wifi0 {
+	brcm,board-type = "apple,azores";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,azores";
+};
+
+&port01 {
+	bus-range = <2 2>;
+
+	status = "okay";
+
+	ethernet0: ethernet@0,0 {
+		reg = <0x20000 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-mac-address = [00 10 18 00 00 00];
+	};
+};
+
+&pcie1_dart {
+	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/apple/t8122-j434.dts b/arch/arm64/boot/dts/apple/t8122-j434.dts
index ead5afd77efb..e2f4880095ab 100644
--- a/arch/arm64/boot/dts/apple/t8122-j434.dts
+++ b/arch/arm64/boot/dts/apple/t8122-j434.dts
@@ -16,4 +16,42 @@
 / {
 	compatible = "apple,j434", "apple,t8122", "apple,arm-platform";
 	model = "Apple iMac (24-inch, 4x USB-C, M3, 2023)";
+
+	aliases {
+		ethernet0 = &ethernet0;
+	};
+};
+
+&wifi0 {
+	brcm,board-type = "apple,iona";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,iona";
+};
+
+&port01 {
+	bus-range = <2 2>;
+
+	status = "okay";
+
+	ethernet0: ethernet@0,0 {
+		reg = <0x20000 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-mac-address = [00 10 18 00 00 00];
+	};
+};
+
+&port02 {
+	bus-range = <3 3>;
+
+	status = "okay";
+};
+
+&pcie1_dart {
+	status = "okay";
+};
+
+&pcie2_dart {
+	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/apple/t8122-j504.dts b/arch/arm64/boot/dts/apple/t8122-j504.dts
index e60ec3039196..9a5951ee28c5 100644
--- a/arch/arm64/boot/dts/apple/t8122-j504.dts
+++ b/arch/arm64/boot/dts/apple/t8122-j504.dts
@@ -32,6 +32,32 @@ led-0 {
 	};
 };
 
+&wifi0 {
+	brcm,board-type = "apple,tresco";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,tresco";
+};
+
+&port01 {
+	/* SD card reader */
+	bus-range = <2 2>;
+
+	status = "okay";
+
+	mmc@0,0 {
+		compatible = "pci17a0,9755";
+		reg = <0x20000 0x0 0x0 0x0 0x0>;
+		cd-inverted;
+		wp-inverted;
+	};
+};
+
+&pcie1_dart {
+	status = "okay";
+};
+
 &fpwm1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/apple/t8122-j613.dts b/arch/arm64/boot/dts/apple/t8122-j613.dts
index 40274a983849..7fdafe803e57 100644
--- a/arch/arm64/boot/dts/apple/t8122-j613.dts
+++ b/arch/arm64/boot/dts/apple/t8122-j613.dts
@@ -31,6 +31,14 @@ led-0 {
 	};
 };
 
+&wifi0 {
+	brcm,board-type = "apple,dnieper";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,dnieper";
+};
+
 &fpwm1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/apple/t8122-j615.dts b/arch/arm64/boot/dts/apple/t8122-j615.dts
index 61833f6d019b..d32686f88b76 100644
--- a/arch/arm64/boot/dts/apple/t8122-j615.dts
+++ b/arch/arm64/boot/dts/apple/t8122-j615.dts
@@ -31,6 +31,14 @@ led-0 {
 	};
 };
 
+&wifi0 {
+	brcm,board-type = "apple,tuzla";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,tuzla";
+};
+
 &fpwm1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi
index 2dbdb77d5413..c184dd94e8c7 100644
--- a/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi
+++ b/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi
@@ -11,7 +11,9 @@
 
 / {
 	aliases {
+		bluetooth0 = &bluetooth0;
 		serial0 = &serial0;
+		wifi0 = &wifi0;
 	};
 
 	chosen {
@@ -22,7 +24,8 @@ chosen {
 		stdout-path = "serial0";
 
 		framebuffer0: framebuffer@0 {
-			compatible = "apple,simple-framebuffer", "simple-framebuffer";
+			compatible = "apple,simple-framebuffer",
+				     "simple-framebuffer";
 			reg = <0 0 0 0>; /* To be filled by loader */
 			power-domains = <&ps_disp_cpu>, <&ps_dptx_ext_phy>;
 			/* Format properties will be added by loader */
@@ -47,3 +50,27 @@ memory@800000000 {
 &serial0 {
 	status = "okay";
 };
+
+/*
+ * Force the bus number assignments so that we can declare some of the
+ * on-board devices and properties that are populated by the bootloader
+ * (such as MAC addresses).
+ */
+&port00 {
+	bus-range = <1 1>;
+
+	wifi0: wifi@0,0 {
+		compatible = "pci14e4,4434";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-mac-address = [00 00 00 00 00 00];
+		apple,antenna-sku = "XX";
+	};
+
+	bluetooth0: bluetooth@0,1 {
+		compatible = "pci14e4,5f72";
+		reg = <0x10100 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-bd-address = [00 00 00 00 00 00];
+	};
+};
diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi
index 959ddf36efa1..241a32dfe011 100644
--- a/arch/arm64/boot/dts/apple/t8122.dtsi
+++ b/arch/arm64/boot/dts/apple/t8122.dtsi
@@ -338,6 +338,14 @@ i2c4_pins: i2c4-pins {
 				pinmux = <APPLE_PINMUX(149, 1)>,
 					 <APPLE_PINMUX(148, 1)>;
 			};
+
+			pcie_pins: pcie-pins {
+				// clkreq pins
+				pinmux = <APPLE_PINMUX(183, 1)>,
+					 <APPLE_PINMUX(184, 1)>,
+					 <APPLE_PINMUX(185, 1)>,
+					 <APPLE_PINMUX(186, 1)>;
+			};
 		};
 
 		pmgr: power-management@2d0700000 {
@@ -494,6 +502,173 @@ nvme: nvme@30dcc0000 {
 
 			apple,sart = <&sart>;
 		};
+
+		pcie0: pcie@580000000 {
+			device_type = "pci";
+			compatible = "apple,t8122-pcie", "apple,t6020-pcie";
+
+			reg = <0x5 0x80000000 0x0 0x1000000>,	/* config */
+			      <0x5 0x91000000 0x0 0x4000>,	/* rc */
+			      <0x5 0x94008000 0x0 0x4000>,	/* port0 */
+			      <0x5 0x95008000 0x0 0x4000>,	/* port1 */
+			      <0x5 0x96008000 0x0 0x4000>,	/* port2 */
+			      <0x5 0x97008000 0x0 0x4000>,	/* port3 */
+			      <0x5 0x9e00c000 0x0 0x4000>,	/* phy0 */
+			      <0x5 0x9e010000 0x0 0x4000>,	/* phy1 */
+			      <0x5 0x9e014000 0x0 0x4000>,	/* phy2 */
+			      <0x5 0x9e018000 0x0 0x4000>;	/* phy3 */
+			reg-names = "config", "rc",
+				    "port0", "port1", "port2", "port3",
+				    "phy0", "phy1", "phy2", "phy3";
+			ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
+				 <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;
+
+			#address-cells = <3>;
+			bus-range = <0 4>;
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 923 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 932 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 941 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 950 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommu-map = <0x100 &pcie0_dart 1 1>,
+				    <0x200 &pcie1_dart 1 1>,
+				    <0x300 &pcie2_dart 1 1>,
+				    <0x400 &pcie3_dart 1 1>;
+			iommu-map-mask = <0xff00>;
+
+			msi-controller;
+			msi-parent = <&pcie0>;
+			msi-ranges = <&aic AIC_IRQ 1075 IRQ_TYPE_EDGE_RISING 32>;
+
+			pinctrl-0 = <&pcie_pins>;
+			pinctrl-names = "default";
+
+			power-domains = <&ps_apcie_gp>;
+
+			#size-cells = <2>;
+
+			port00: pci@0,0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
+						<0 0 0 2 &port00 0 0 0 1>,
+						<0 0 0 3 &port00 0 0 0 2>,
+						<0 0 0 4 &port00 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+
+				reset-gpios = <&pinctrl_ap 187 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+			};
+
+			port01: pci@1,0 {
+				device_type = "pci";
+				reg = <0x800 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
+						<0 0 0 2 &port01 0 0 0 1>,
+						<0 0 0 3 &port01 0 0 0 2>,
+						<0 0 0 4 &port01 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+
+				reset-gpios = <&pinctrl_ap 188 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+
+				status = "disabled";
+			};
+
+			port02: pci@2,0 {
+				device_type = "pci";
+				reg = <0x1000 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
+						<0 0 0 2 &port02 0 0 0 1>,
+						<0 0 0 3 &port02 0 0 0 2>,
+						<0 0 0 4 &port02 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+
+				reset-gpios = <&pinctrl_ap 189 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+
+				status = "disabled";
+			};
+
+			port03: pci@3,0 {
+				device_type = "pci";
+				reg = <0x1800 0x0 0x0 0x0 0x0>;
+				ranges;
+				#address-cells = <3>;
+
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
+						<0 0 0 2 &port03 0 0 0 1>,
+						<0 0 0 3 &port03 0 0 0 2>,
+						<0 0 0 4 &port03 0 0 0 3>;
+				interrupt-map-mask = <0 0 0 7>;
+
+				reset-gpios = <&pinctrl_ap 190 GPIO_ACTIVE_LOW>;
+				#size-cells = <2>;
+
+				status = "disabled";
+			};
+		};
+
+		pcie0_dart: iommu@594000000 {
+			compatible = "apple,t8122-dart", "apple,t8110-dart";
+			reg = <0x5 0x94000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 924 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_gp>;
+		};
+
+		pcie1_dart: iommu@595000000 {
+			compatible = "apple,t8122-dart", "apple,t8110-dart";
+			reg = <0x5 0x95000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 933 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_gp>;
+
+			status = "disabled";
+		};
+
+		pcie2_dart: iommu@596000000 {
+			compatible = "apple,t8122-dart", "apple,t8110-dart";
+			reg = <0x5 0x96000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 942 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_gp>;
+
+			status = "disabled";
+		};
+
+		pcie3_dart: iommu@597000000 {
+			compatible = "apple,t8122-dart", "apple,t8110-dart";
+			reg = <0x5 0x97000000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 951 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			power-domains = <&ps_apcie_gp>;
+
+			status = "disabled";
+		};
 	};
 
 	timer {

-- 
2.56.0

[PATCH v2 6/7] arm64: dts: apple: t603x-j514-j516: Add PCIe device nodes

[Janne Grunau]

From: Yureka Lilian <yureka@cyberchaos.dev>

Add WiFi, Bluetooth and SD-Card reader device nodes to all M3 Pro and
Max Macbook Pros.
The bootloader will fill MAC addresses for the network devices, add
Wifi and Bluetooth calibration data and set "apple,antenna-sku".

Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
Signed-off-by: Janne Grunau <j@jannau.net>

---
Changes in v2:
- fix copy'n'pated error in WiFi/Bluetooth PCI device compatibles,
  adjust to BCM4388 used on this devices
---
 arch/arm64/boot/dts/apple/t6030-j514s.dts      |  8 +++++
 arch/arm64/boot/dts/apple/t6030-j516s.dts      |  8 +++++
 arch/arm64/boot/dts/apple/t6031-j514c.dts      |  8 +++++
 arch/arm64/boot/dts/apple/t6031-j516c.dts      |  8 +++++
 arch/arm64/boot/dts/apple/t6034-j514m.dts      |  8 +++++
 arch/arm64/boot/dts/apple/t6034-j516m.dts      |  8 +++++
 arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi | 41 ++++++++++++++++++++++++++
 7 files changed, 89 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6030-j514s.dts b/arch/arm64/boot/dts/apple/t6030-j514s.dts
index 3ba2c9ca4347..f7c1307e76bd 100644
--- a/arch/arm64/boot/dts/apple/t6030-j514s.dts
+++ b/arch/arm64/boot/dts/apple/t6030-j514s.dts
@@ -20,3 +20,11 @@ / {
 &framebuffer0 {
 	power-domains = <&ps_disp_cpu>;
 };
+
+&wifi0 {
+	brcm,board-type = "apple,texa";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,texa";
+};
diff --git a/arch/arm64/boot/dts/apple/t6030-j516s.dts b/arch/arm64/boot/dts/apple/t6030-j516s.dts
index ab07bf7939ab..9f9609575ed0 100644
--- a/arch/arm64/boot/dts/apple/t6030-j516s.dts
+++ b/arch/arm64/boot/dts/apple/t6030-j516s.dts
@@ -20,3 +20,11 @@ / {
 &framebuffer0 {
 	power-domains = <&ps_disp_cpu>;
 };
+
+&wifi0 {
+	brcm,board-type = "apple,jura";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,jura";
+};
diff --git a/arch/arm64/boot/dts/apple/t6031-j514c.dts b/arch/arm64/boot/dts/apple/t6031-j514c.dts
index c1507158325e..8cc2224ee0fd 100644
--- a/arch/arm64/boot/dts/apple/t6031-j514c.dts
+++ b/arch/arm64/boot/dts/apple/t6031-j514c.dts
@@ -16,3 +16,11 @@ / {
 	compatible = "apple,j514c", "apple,t6031", "apple,arm-platform";
 	model = "Apple MacBook Pro (14-inch, M3 Max, 16 CPU cores, Nov 2023)";
 };
+
+&wifi0 {
+	brcm,board-type = "apple,texa";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,texa";
+};
diff --git a/arch/arm64/boot/dts/apple/t6031-j516c.dts b/arch/arm64/boot/dts/apple/t6031-j516c.dts
index 841b2bb10b06..5dfe886d47a9 100644
--- a/arch/arm64/boot/dts/apple/t6031-j516c.dts
+++ b/arch/arm64/boot/dts/apple/t6031-j516c.dts
@@ -16,3 +16,11 @@ / {
 	compatible = "apple,j516c", "apple,t6031", "apple,arm-platform";
 	model = "Apple MacBook Pro (16-inch, M3 Max, 16 CPU cores, Nov 2023)";
 };
+
+&wifi0 {
+	brcm,board-type = "apple,jura";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,jura";
+};
diff --git a/arch/arm64/boot/dts/apple/t6034-j514m.dts b/arch/arm64/boot/dts/apple/t6034-j514m.dts
index e31bd0bc0592..dfae771ec626 100644
--- a/arch/arm64/boot/dts/apple/t6034-j514m.dts
+++ b/arch/arm64/boot/dts/apple/t6034-j514m.dts
@@ -16,3 +16,11 @@ / {
 	compatible = "apple,j514m", "apple,t6034", "apple,arm-platform";
 	model = "Apple MacBook Pro (14-inch, M3 Max, 14 CPU cores, Nov 2023)";
 };
+
+&wifi0 {
+	brcm,board-type = "apple,texa";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,texa";
+};
diff --git a/arch/arm64/boot/dts/apple/t6034-j516m.dts b/arch/arm64/boot/dts/apple/t6034-j516m.dts
index 4d6513558597..dc5c202a787b 100644
--- a/arch/arm64/boot/dts/apple/t6034-j516m.dts
+++ b/arch/arm64/boot/dts/apple/t6034-j516m.dts
@@ -16,3 +16,11 @@ / {
 	compatible = "apple,j516m", "apple,t6034", "apple,arm-platform";
 	model = "Apple MacBook Pro (16-inch, M3 Max, 14 CPU cores, Nov 2023)";
 };
+
+&wifi0 {
+	brcm,board-type = "apple,jura";
+};
+
+&bluetooth0 {
+	brcm,board-type = "apple,jura";
+};
diff --git a/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi b/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi
index bbee373044f9..a3e4e5d734c6 100644
--- a/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi
+++ b/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi
@@ -21,7 +21,9 @@ / {
 	chassis-type = "laptop";
 
 	aliases {
+		bluetooth0 = &bluetooth0;
 		serial0 = &serial0;
+		wifi0 = &wifi0;
 	};
 
 	chosen {
@@ -67,3 +69,42 @@ &serial0 {
 &fpwm0 {
 	status = "okay";
 };
+
+/* PCIe devices */
+
+/*
+ * Force the bus number assignments so that we can declare some of the
+ * on-board devices and properties that are populated by the bootloader
+ * (such as MAC addresses).
+ */
+&port00 {
+	/* WLAN */
+	bus-range = <1 1>;
+
+	wifi0: wifi@0,0 {
+		compatible = "pci14e4,4434";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-mac-address = [00 10 18 00 00 10];
+		apple,antenna-sku = "XX";
+	};
+
+	bluetooth0: bluetooth@0,1 {
+		compatible = "pci14e4,5f72";
+		reg = <0x10100 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-bd-address = [00 00 00 00 00 00];
+	};
+};
+
+&port01 {
+	/* SD card reader */
+	bus-range = <2 2>;
+
+	mmc@0,0 {
+		compatible = "pci17a0,9755";
+		reg = <0x20000 0x0 0x0 0x0 0x0>;
+		cd-inverted;
+		wp-inverted;
+	};
+};

-- 
2.56.0

[PATCH v2 7/7] arm64: dts: apple: t6032-j575d: Add PCIe device nodes

[Janne Grunau]

Add WiFi, Bluetooth, SD-Card reader, ethernet NIC and USB xHCI device
nodes for M3 Ultra Mac Studio.
The bootloader will fill MAC addresses for the network devices, add
Wifi and Bluetooth calibration data and set "apple,antenna-sku".

Signed-off-by: Janne Grunau <j@jannau.net>

---
Changes in v2:
- fix copy'n'pated error in WiFi/Bluetooth PCI device compatibles,
  adjust to BCM4388 used on this devices
---
 arch/arm64/boot/dts/apple/t6032-j575d.dts | 72 +++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6032-j575d.dts b/arch/arm64/boot/dts/apple/t6032-j575d.dts
index 12991546d4bb..902fd90c25a5 100644
--- a/arch/arm64/boot/dts/apple/t6032-j575d.dts
+++ b/arch/arm64/boot/dts/apple/t6032-j575d.dts
@@ -16,7 +16,10 @@ / {
 	model = "Apple Mac Studio (M3 Ultra, 2025)";
 
 	aliases {
+		bluetooth0 = &bluetooth0;
+		ethernet0 = &ethernet0;
 		serial0 = &serial0;
+		wifi0 = &wifi0;
 	};
 
 	chosen {
@@ -46,3 +49,72 @@ memory@10000000000 {
 &serial0 {
 	status = "okay";
 };
+
+/* PCIe devices */
+
+/*
+ * Force the bus number assignments so that we can declare some of the
+ * on-board devices and properties that are populated by the bootloader
+ * (such as MAC addresses).
+ */
+&port00 {
+	/* WLAN */
+	bus-range = <1 1>;
+
+	wifi0: wifi@0,0 {
+		compatible = "pci14e4,4434";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-mac-address = [00 10 18 00 00 10];
+		apple,antenna-sku = "XX";
+		brcm,board-type = "apple,aruba";
+	};
+
+	bluetooth0: bluetooth@0,1 {
+		compatible = "pci14e4,5f72";
+		reg = <0x10100 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-bd-address = [00 00 00 00 00 00];
+		brcm,board-type = "apple,aruba";
+	};
+};
+
+&port01 {
+	/* SD card reader */
+	bus-range = <2 2>;
+
+	mmc@0,0 {
+		compatible = "pci17a0,9755";
+		reg = <0x20000 0x0 0x0 0x0 0x0>;
+		cd-inverted;
+		wp-inverted;
+	};
+};
+
+&port02 {
+	/* AQC113 10 Gbit Ethernet */
+	bus-range = <3 3>;
+	status = "okay";
+
+	ethernet0: ethernet@0,0 {
+		compatible = "pci1d6a,04c0";
+		reg = <0x30000 0x0 0x0 0x0 0x0>;
+		/* To be filled by the loader */
+		local-mac-address = [00 10 18 00 00 00];
+	};
+};
+
+&port03 {
+	/* USB xHCI */
+	bus-range = <4 4>;
+	status = "okay";
+};
+
+
+&pcie0_dart_2 {
+	status = "okay";
+};
+
+&pcie0_dart_3 {
+	status = "okay";
+};

-- 
2.56.0

Re: [PATCH v2 3/7] arm64: dts: apple: t6030: Add PCIe nodes

[sashiko-bot]

> Add the PCIe controller, its ports, IOMMUs and clock request pins to the
> base M3 Pro .dtsi file.
> M3 Pro is only used in 14 and 16-inch Macbook Pro which connect PCIe
> devices to the port 0 and 1.
> 
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=3

Re: [PATCH v2 4/7] arm64: dts: apple: t6031: Add PCIe nodes

[sashiko-bot]

> From: Yureka Lilian <yureka@cyberchaos.dev>
> 
> Add the PCIe controller, its ports, IOMMUs and clock request pins to the
> die0 M3 Max/Ultra .dtsi file.
> All M3 Max and Ultra devices use port 0 and 1 so enable them and their
> IOMMU.
> 
> Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
> Co-developed-by: Janne Grunau <j@jannau.net>
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=4

Re: [PATCH v2 1/7] arm64: dts: apple: t8122: Keep ps_apcie_phy_sw always-on

[sashiko-bot]

> The APCIE_PHY_SW power state is in Apple's device tree a child of the
> virtual storage and general purpose PCIe power-states. MacOS however
> keeps it always powered on. Mirror this behaviour like the M2 Pro/Max
> device trees already do in t602x-pgmr.dtsi.
> 
> Fixes: c65ab4905e58 ("arm64: dts: apple: Initial t8122 (M3) device trees")
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=1

Re: [PATCH v2 2/7] dt-bindings: PCI: apple,pcie: Add M3 generation compatibles

[sashiko-bot]

> The PCIe controller on Apple M3, M3 Pro, Max and Ultra SoCs are
> compatible with the one on M2 Pro and Max. Add their per SoC compatibles
> "apple,t8122-pcie" (M3), "apple,t6030-pcie" (M3 Pro) and
> "apple,t6031-pcie" (M3 Max/Ultra) to the bindings.
> 
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=2

Re: [PATCH v2 5/7] arm64: dts: apple: t8122: Add PCIe device nodes

[sashiko-bot]

> From: Alyssa Milburn <amilburn@zall.org>
> 
> Add the PCIe controller, its ports, IOMMUs and clock request pins to the
> base M3 Pro .dtsi file.
> 
> Add PCIe devices for WiFi, Bluetooth, Ethernet, SD-Card reader and USB
> xHCI to device trees and enable their ports and IOMMU if necessary.
> The bootloader will fill MAC addresses and calibration data properties
> in their device nodes.
> 
> Signed-off-by: Alyssa Milburn <amilburn@zall.org>
> Co-developed-by: Michael Reeves <michael.reeves077@gmail.com>
> Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=5

Re: [PATCH v2 7/7] arm64: dts: apple: t6032-j575d: Add PCIe device nodes

[sashiko-bot]

> Add WiFi, Bluetooth, SD-Card reader, ethernet NIC and USB xHCI device
> nodes for M3 Ultra Mac Studio.
> The bootloader will fill MAC addresses for the network devices, add
> Wifi and Bluetooth calibration data and set "apple,antenna-sku".
> 
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=7

Re: [PATCH v2 6/7] arm64: dts: apple: t603x-j514-j516: Add PCIe device nodes

[sashiko-bot]

> From: Yureka Lilian <yureka@cyberchaos.dev>
> 
> Add WiFi, Bluetooth and SD-Card reader device nodes to all M3 Pro and
> Max Macbook Pros.
> The bootloader will fill MAC addresses for the network devices, add
> Wifi and Bluetooth calibration data and set "apple,antenna-sku".
> 
> Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
> Signed-off-by: Janne Grunau <j@jannau.net>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-apple-m3-pcie-v2-0-0e5ffec71da4@jannau.net?part=6

Re: [PATCH v2 2/7] dt-bindings: PCI: apple,pcie: Add M3 generation compatibles

[Krzysztof Kozlowski]

On Sun, Nov 08, 2026 at 03:22:36PM +0100, Janne Grunau wrote:
> The PCIe controller on Apple M3, M3 Pro, Max and Ultra SoCs are
> compatible with the one on M2 Pro and Max. Add their per SoC compatibles
> "apple,t8122-pcie" (M3), "apple,t6030-pcie" (M3 Pro) and
> "apple,t6031-pcie" (M3 Max/Ultra) to the bindings.
> 
> Signed-off-by: Janne Grunau <j@jannau.net>
> 
> ---
> Changes in v2:
> - modified subject line
> ---
>  Documentation/devicetree/bindings/pci/apple,pcie.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof