* [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number
2026-11-10 22:48 [PATCH v5 0/3] Fix amdgpu detection of pci=realloc Mario Limonciello
@ 2026-11-10 22:48 ` Mario Limonciello
2026-11-11 2:18 ` sashiko-bot
2026-11-11 13:18 ` Lazar, Lijo
2026-11-10 22:48 ` [PATCH v5 2/3] drm/amdgpu: Match VFCT using initial PCI " Mario Limonciello
2026-11-10 22:48 ` [PATCH v5 3/3] drm/radeon: " Mario Limonciello
2 siblings, 2 replies; 8+ messages in thread
From: Mario Limonciello @ 2026-11-10 22:48 UTC (permalink / raw)
To: Bjorn Helgaas, Alex Deucher, Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel,
Mario Limonciello
Bridge scans are split into two passes when bus numbers need reassigning.
Save the firmware secondary bus number on the bridge pci_dev during pass 0,
before the bridge is disabled, and keep it for pass 1 so devices discovered
there can read the original bus number via their upstream bridge.
Guard the cached value with a validity flag so later rescans do not overwrite
it with the renumbered runtime value.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/pci/probe.c | 4 ++++
include/linux/pci.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 27008e2ea5afc..14b3dd7dac271 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1418,6 +1418,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
secondary, subordinate, pass);
+ if (!pass && !dev->fw_sec_busnr_valid) {
+ dev->fw_sec_busnr = secondary;
+ dev->fw_sec_busnr_valid = true;
+ }
if (!primary && (primary != bus->number) && secondary && subordinate) {
pci_warn(dev, "Primary bus is hard wired to 0\n");
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 5ffcf5ce8c966..b942dbb4edf57 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -363,6 +363,8 @@ struct pci_dev {
struct pci_slot *slot; /* Physical slot this device is in */
unsigned int devfn; /* Encoded device & function index */
+ /* Firmware secondary bus number saved across bridge scan passes */
+ unsigned char fw_sec_busnr;
unsigned short vendor;
unsigned short device;
unsigned short subsystem_vendor;
@@ -414,6 +416,7 @@ struct pci_dev {
unsigned int pme_poll:1; /* Poll device's PME status bit */
unsigned int pinned:1; /* Whether this dev is pinned */
unsigned int config_rrs_sv:1; /* Config RRS software visibility */
+ unsigned int fw_sec_busnr_valid:1;
unsigned int imm_ready:1; /* Supports Immediate Readiness */
unsigned int d1_support:1; /* Low power state D1 is supported */
unsigned int d2_support:1; /* Low power state D2 is supported */
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number
2026-11-10 22:48 ` [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
@ 2026-11-11 2:18 ` sashiko-bot
2026-11-11 13:18 ` Lazar, Lijo
1 sibling, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-11-11 2:18 UTC (permalink / raw)
To: Mario Limonciello; +Cc: linux-pci, dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] PCI: unconfigured secondary bus 0 cached as valid in
pci_scan_bridge_extend()
--
commit fd23152db632066be6cd9884f50d5722e11a3151
Author: Mario Limonciello <mario.limonciello@amd.com>
PCI: Cache bridge firmware secondary bus number
This commit caches a bridge's firmware-assigned secondary bus number on
struct pci_dev during pass 0 of bridge scanning so devices enumerated in
pass 1 can still access the original bus number after renumbering.
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 27008e2ea5afc..14b3dd7dac271 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1418,6 +1418,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
>
> pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
> secondary, subordinate, pass);
> + if (!pass && !dev->fw_sec_busnr_valid) {
> + dev->fw_sec_busnr = secondary;
> + dev->fw_sec_busnr_valid = true;
> + }
[Severity: Medium]
Does this mark dev->fw_sec_busnr_valid as true even when secondary is 0
(unconfigured by firmware or hot-plugged) or 0xff (failed config read)?
Bus 0 is the root bus and is never a valid secondary bus behind a bridge.
When firmware leaves a bridge unconfigured for pass 1 to assign, this caches
dev->fw_sec_busnr = 0 with dev->fw_sec_busnr_valid = true, so consumers
checking bridge->fw_sec_busnr_valid will use bus 0 instead of falling back
to pdev->bus->number.
Note that simply gating this assignment on secondary > 0 && secondary < 0xff
would leave dev->fw_sec_busnr_valid false on an initially unconfigured
bridge, allowing a later rescan to cache the runtime-assigned bus number, so
tracking whether pass 0 has already run may need to be separate from whether
fw_sec_busnr is valid.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261110-vfct-regression-v5-0-f49fae981bf3@amd.com?part=1
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number
2026-11-10 22:48 ` [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
2026-11-11 2:18 ` sashiko-bot
@ 2026-11-11 13:18 ` Lazar, Lijo
1 sibling, 0 replies; 8+ messages in thread
From: Lazar, Lijo @ 2026-11-11 13:18 UTC (permalink / raw)
To: Mario Limonciello, Bjorn Helgaas, Alex Deucher,
Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel
On 11-Nov-26 4:18 AM, Mario Limonciello wrote:
> Bridge scans are split into two passes when bus numbers need reassigning.
> Save the firmware secondary bus number on the bridge pci_dev during pass 0,
> before the bridge is disabled, and keep it for pass 1 so devices discovered
> there can read the original bus number via their upstream bridge.
>
> Guard the cached value with a validity flag so later rescans do not overwrite
> it with the renumbered runtime value.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/pci/probe.c | 4 ++++
> include/linux/pci.h | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 27008e2ea5afc..14b3dd7dac271 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1418,6 +1418,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
>
> pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
> secondary, subordinate, pass);
> + if (!pass && !dev->fw_sec_busnr_valid) {
> + dev->fw_sec_busnr = secondary;
> + dev->fw_sec_busnr_valid = true;
> + }
I think the original suggestion from Bjorn was to save it inside
pci_read_bridge_windows() which happens before the two pass scan. In
that case, it doesn't need the extra flag or checks.
Thanks,
Lijo
>
> if (!primary && (primary != bus->number) && secondary && subordinate) {
> pci_warn(dev, "Primary bus is hard wired to 0\n");
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 5ffcf5ce8c966..b942dbb4edf57 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -363,6 +363,8 @@ struct pci_dev {
> struct pci_slot *slot; /* Physical slot this device is in */
>
> unsigned int devfn; /* Encoded device & function index */
> + /* Firmware secondary bus number saved across bridge scan passes */
> + unsigned char fw_sec_busnr;
> unsigned short vendor;
> unsigned short device;
> unsigned short subsystem_vendor;
> @@ -414,6 +416,7 @@ struct pci_dev {
> unsigned int pme_poll:1; /* Poll device's PME status bit */
> unsigned int pinned:1; /* Whether this dev is pinned */
> unsigned int config_rrs_sv:1; /* Config RRS software visibility */
> + unsigned int fw_sec_busnr_valid:1;
> unsigned int imm_ready:1; /* Supports Immediate Readiness */
> unsigned int d1_support:1; /* Low power state D1 is supported */
> unsigned int d2_support:1; /* Low power state D2 is supported */
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 2/3] drm/amdgpu: Match VFCT using initial PCI bus number
2026-11-10 22:48 [PATCH v5 0/3] Fix amdgpu detection of pci=realloc Mario Limonciello
2026-11-10 22:48 ` [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
@ 2026-11-10 22:48 ` Mario Limonciello
2026-11-10 22:59 ` sashiko-bot
2026-11-10 22:48 ` [PATCH v5 3/3] drm/radeon: " Mario Limonciello
2 siblings, 1 reply; 8+ messages in thread
From: Mario Limonciello @ 2026-11-10 22:48 UTC (permalink / raw)
To: Bjorn Helgaas, Alex Deucher, Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel,
Mario Limonciello, Reza Nikzad Chaleshori
VFCT records the PCI bus number from BIOS POST. The current bus number
can change after PCI core renumbers the bus, while accepting a mismatch
based only on device identity can select the wrong VFCT image when
matching devices are present. Compare against the bus number captured
from the firmware bus assignment before bridge renumbering.
Reported-by: Reza Nikzad Chaleshori <rezanikzadch@gmail.com>
Closes: https://lore.kernel.org/amd-gfx/20261014080523.186533-1-rezanikzadch@gmail.com/
Fixes: 11c141672045f ("drm/amdgpu: Fix VFCT bus number matching with soft filter")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 08ed1eb695586..a562265eafd26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -386,16 +386,17 @@ static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
* VFCT entries contain the PCI bus number as recorded during BIOS POST.
* On systems where the kernel renumbers PCI buses (e.g. pci=realloc or
* resource conflicts), the runtime bus number may differ from the POST
- * value. Match by device identity (vendor + device + function) and use
- * the bus number as a preference: exact bus match is preferred, but when
- * the bus numbers disagree we accept the entry if the device identity
- * matches.
+ * value. Match using the bus number captured when the device was
+ * discovered, before any bus renumbering.
*
* Returns: 0 on match, -ENODEV on no match
*/
static int amdgpu_acpi_vfct_match(struct amdgpu_device *adev,
VFCT_IMAGE_HEADER *vhdr)
{
+ struct pci_dev *bridge = adev->pdev->bus->self;
+ unsigned char initial_bus;
+
/* Vendor and device IDs must always match */
if (vhdr->VendorID != adev->pdev->vendor ||
vhdr->DeviceID != adev->pdev->device)
@@ -405,16 +406,12 @@ static int amdgpu_acpi_vfct_match(struct amdgpu_device *adev,
vhdr->PCIFunction != PCI_FUNC(adev->pdev->devfn))
return -ENODEV;
- /* Exact bus number match - preferred */
- if (vhdr->PCIBus == adev->pdev->bus->number)
- return 0;
+ if (bridge && bridge->fw_sec_busnr_valid)
+ initial_bus = bridge->fw_sec_busnr;
+ else
+ initial_bus = adev->pdev->bus->number;
- /* Bus mismatch but device identity matches (PCI renumbering case) */
- dev_notice(adev->dev,
- "VFCT bus number mismatch: table %u != runtime %u, matching by device identity (vendor 0x%04x device 0x%04x)\n",
- vhdr->PCIBus, adev->pdev->bus->number,
- adev->pdev->vendor, adev->pdev->device);
- return 0;
+ return vhdr->PCIBus == initial_bus ? 0 : -ENODEV;
}
static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v5 3/3] drm/radeon: Match VFCT using initial PCI bus number
2026-11-10 22:48 [PATCH v5 0/3] Fix amdgpu detection of pci=realloc Mario Limonciello
2026-11-10 22:48 ` [PATCH v5 1/3] PCI: Cache bridge firmware secondary bus number Mario Limonciello
2026-11-10 22:48 ` [PATCH v5 2/3] drm/amdgpu: Match VFCT using initial PCI " Mario Limonciello
@ 2026-11-10 22:48 ` Mario Limonciello
2026-11-10 22:56 ` sashiko-bot
2 siblings, 1 reply; 8+ messages in thread
From: Mario Limonciello @ 2026-11-10 22:48 UTC (permalink / raw)
To: Bjorn Helgaas, Alex Deucher, Christian König
Cc: Oz Tiram, linux-pci, linux-kernel, amd-gfx, dri-devel,
Mario Limonciello
VFCT records the PCI bus number from BIOS POST. The current bus number
can change after PCI core renumbers the bus, while accepting a mismatch
based only on device identity can select the wrong VFCT image when
matching devices are present. Compare against the bus number captured
from the firmware bus assignment before bridge renumbering.
Fixes: 4059e2f02c8a ("drm/radeon: Fix VFCT bus number matching with soft filter")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/gpu/drm/radeon/radeon_bios.c | 25 +++++++++++--------------
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 1da6bf1c17ff3..e888c8986d7bd 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -609,16 +609,17 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
* VFCT entries contain the PCI bus number as recorded during BIOS POST.
* On systems where the kernel renumbers PCI buses (e.g. pci=realloc or
* resource conflicts), the runtime bus number may differ from the POST
- * value. Match by device identity (vendor + device + function) and use
- * the bus number as a preference: exact bus match is preferred, but when
- * the bus numbers disagree we accept the entry if the device identity
- * matches.
+ * value. Match using the bus number captured when the device was
+ * discovered, before any bus renumbering.
*
* Returns: 0 on match, -ENODEV on no match
*/
static int radeon_acpi_vfct_match(struct radeon_device *rdev,
- VFCT_IMAGE_HEADER *vhdr)
+ VFCT_IMAGE_HEADER *vhdr)
{
+ struct pci_dev *bridge = rdev->pdev->bus->self;
+ unsigned char initial_bus;
+
/* Vendor and device IDs must always match */
if (vhdr->VendorID != rdev->pdev->vendor ||
vhdr->DeviceID != rdev->pdev->device)
@@ -628,16 +629,12 @@ static int radeon_acpi_vfct_match(struct radeon_device *rdev,
vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn))
return -ENODEV;
- /* Exact bus number match - preferred */
- if (vhdr->PCIBus == rdev->pdev->bus->number)
- return 0;
+ if (bridge && bridge->fw_sec_busnr_valid)
+ initial_bus = bridge->fw_sec_busnr;
+ else
+ initial_bus = rdev->pdev->bus->number;
- /* Bus mismatch but device identity matches (PCI renumbering case) */
- dev_notice(&rdev->pdev->dev,
- "VFCT bus number mismatch: table %u != runtime %u, matching by device identity (vendor 0x%04x device 0x%04x)\n",
- vhdr->PCIBus, rdev->pdev->bus->number,
- rdev->pdev->vendor, rdev->pdev->device);
- return 0;
+ return vhdr->PCIBus == initial_bus ? 0 : -ENODEV;
}
static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread