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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [RESEND Patch v10 06/23] x86/fpu/xstate: Add xsaves_nmi() helper
Date: Tue, 25 Aug 2026 09:03:14 +0800	[thread overview]
Message-ID: <029473ae-0bee-4e67-9bdf-1855ec8e2410@linux.intel.com> (raw)
In-Reply-To: <20260824085408.595F21F000E9@smtp.kernel.org>


On 8/24/2026 4:54 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Critical] xsaves_nmi() uses the XSAVES instruction which employs hardware 'modified optimization', causing catastrophic data corruption for the interrupted task.
> --
>
> --- Patch [6]: [RESEND Patch v10 06/23] x86/fpu/xstate: Add xsaves_nmi() helper ---
> commit 2691ef22b25df7392d6766bb1de8a6d97a6ee37c
> Author: Kan Liang <kan.liang@linux.intel.com>
>
>     x86/fpu/xstate: Add xsaves_nmi() helper
>
> This commit introduces the xsaves_nmi() helper function to allow the perf
> subsystem to save supported xsave states within an NMI handler. It is intended
> to snapshot SIMD and APX eGPR registers at the exact moment an NMI occurs.
>
>> diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
>> index a7b6524a9dea2..d39c01546dee7 100644
>> --- a/arch/x86/kernel/fpu/xstate.c
>> +++ b/arch/x86/kernel/fpu/xstate.c
> [ ... ]
>> @@ -1474,6 +1474,29 @@ void xrstors(struct xregs_state *xstate, u64 mask)
> [ ... ]
>> +void xsaves_nmi(struct xregs_state *xstate, u64 mask)
>> +{
>> +	int err;
>> +
>> +	if (!in_nmi())
>> +		return;
>> +
>> +	XSTATE_OP(XSAVES, xstate, (u32)mask, (u32)(mask >> 32), err);
> [Severity: Critical]
> Does executing the xsaves instruction in this context corrupt the FPU state of
> the interrupted task?
>
> According to the Intel SDM, the xsaves instruction employs a modified
> optimization that unconditionally resets the CPU internal state-component
> tracking, marking all components as unmodified.
>
> If a task is interrupted by an NMI (such as a perf PMI) and this instruction
> executes, won't the subsequent context switch out of the task also see the
> state as unmodified? It seems the normal context-switch xsaves would silently
> skip saving the state to the task FPU buffer, losing any SIMD modifications
> made prior to the NMI.
>
> Additionally, since xsaves skips writing components it considers unmodified,
> could this leak stale SIMD state from previously interrupted tasks into the
> current perf sample buffer?

No, modified optimization is bound with the xstate buffer. Currently perf
use xsaves_nmi() with an dedicated xstate buffer and each sampling xstate
would be cleared before calling the xsaves_nmi(). So it won't impact other
xsaves usages and leak the stale xstate information.

Thanks.


>
>> +	WARN_ON_ONCE(err);
>> +}

  reply	other threads:[~2026-08-25  1:03 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  8:27 [RESEND Patch v10 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-08-24  8:27 ` [RESEND Patch v10 01/23] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-08-24  8:44   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 02/23] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-08-24  8:52   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 03/23] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-08-24  8:46   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 04/23] perf: Eliminate duplicate arch-specific function definitions Dapeng Mi
2026-08-24  8:44   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 05/23] perf/x86: Use x86_perf_regs in NMI handlers Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 06/23] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-25  1:03     ` Mi, Dapeng [this message]
2026-08-24  8:27 ` [RESEND Patch v10 07/23] x86/fpu: Add update_fpu_state_and_flag() helper Dapeng Mi
2026-08-24  8:47   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 08/23] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-08-24  8:47   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 09/23] perf/x86/intel: Centralize PERF_PMU_CAP_EXTENDED_REGS updates Dapeng Mi
2026-08-24  8:46   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 10/23] perf/x86: Enable XMM register sampling for non-PEBS events Dapeng Mi
2026-08-24  8:53   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 11/23] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-08-24 10:16   ` sashiko-bot
2026-08-25  1:13     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 12/23] perf: Add sampling support for SIMD registers Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-25  1:19     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 13/23] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-08-24  9:12   ` sashiko-bot
2026-08-25  1:28     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 14/23] perf/x86: Support YMM " Dapeng Mi
2026-08-24  8:55   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 15/23] perf/x86: Support ZMM " Dapeng Mi
2026-08-24  8:58   ` sashiko-bot
2026-08-25  1:30     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 16/23] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 17/23] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-08-24  8:56   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 18/23] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-08-24  8:59   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 19/23] perf/x86: Support SSP " Dapeng Mi
2026-08-24  9:39   ` sashiko-bot
2026-08-25  1:34     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 20/23] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs sampling Dapeng Mi
2026-08-24  9:09   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 21/23] perf/x86/intel: Advertise PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-08-24  9:25   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 22/23] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-08-24  9:06   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 23/23] perf/x86/intel: Add sanity check for PEBS record/fragment size Dapeng Mi
2026-08-24  9:08   ` sashiko-bot
2026-08-25  1:39     ` Mi, Dapeng
2026-09-01  8:55 ` [RESEND Patch v10 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Mi, Dapeng
2026-09-02 11:56   ` Peter Zijlstra
2026-09-02 12:13     ` Mi, Dapeng

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