Re: [Patch v3 3/8] perf/x86/intel: Fallback to sw branch type decoding if no hw decoding

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 6/15/2026 9:00 AM, Mi, Dapeng wrote:
> On 6/12/2026 5:21 PM, sashiko-bot@kernel.org wrote:
>> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>> - [High] The patch introduces a severe performance regression in NMI context on Arch LBR CPUs that lack hardware branch-type decoding by unintentionally forcing software disassembly on all recorded branches.
>> --
>>
>> commit 4686077e19d211c998cc542c03a674a17408e8d7
>> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>>
>> perf/x86/intel: Fallback to sw branch type decoding if no hw decoding
>>
>> This commit updates the arch-LBR filtering logic to fallback to software
>> branch-type decoding if hardware decoding is not supported. It replaces
>> the X86_FEATURE_ARCH_LBR CPU feature check with the x86_lbr_type static
>> branch to properly handle arch-LBR configurations that lack branch-type
>> information.
>>
>>> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
>>> index 72f2adcda7c68..e2657f791e507 100644
>>> --- a/arch/x86/events/intel/lbr.c
>>> +++ b/arch/x86/events/intel/lbr.c
>>> @@ -1231,7 +1231,7 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
>>>  		 * Doesn't support OTHER_BRANCH decoding for now.
>>>  		 * OTHER_BRANCH branch type still rely on software decoding.
>>>  		 */
>>> -		if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
>>> +		if (static_branch_likely(&x86_lbr_type) &&
>>>  		    type <= ARCH_LBR_BR_TYPE_KNOWN_MAX) {
>>>  			to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
>>>  			type = arch_lbr_br_type_map[type] | to_plm;
>> [Severity: High]
>> Does this introduce a performance regression in NMI context on arch-LBR CPUs
>> that lack hardware branch-type decoding?
>>
>> Currently, intel_pmu_setup_hw_lbr_filter() unconditionally sets
>> X86_BR_TYPE_SAVE for arch-LBR CPUs:
>>
>> arch/x86/events/intel/lbr.c:intel_pmu_setup_hw_lbr_filter() {
>>     ...
>>     reg->reg |= X86_BR_TYPE_SAVE;
>>     ...
>> }
>>
>> Because X86_BR_TYPE_SAVE is forcibly set in br_sel, the fast-path early
>> return at the start of intel_pmu_lbr_filter() is bypassed even if the user
>> only requested basic branch recording without branch types.
>>
>> With this patch, if x86_lbr_type is false, the loop falls through to the
>> else block and calls branch_type() for every LBR entry. This causes
>> expensive software instruction decoding to unconditionally execute for all
>> LBR records on every PMU interrupt.
>>
>> Should intel_pmu_setup_hw_lbr_filter() be updated to only force-enable
>> X86_BR_TYPE_SAVE if static_branch_likely(&x86_lbr_type) is true?
> AMD guys have known the issue, they would post the fix separately. Thanks.

Please ignore this comment, it should be the comment for next patch. Thanks.


>
>
>