Re: [RFC PATCH v3 0/4] mm/damon: introduce perf event based access check

[SeongJae Park <sj@kernel.org>]

On Wed, 29 Apr 2026 01:00:50 -0700 Namhyung Kim <namhyung@kernel.org> wrote:

> Hello,
> 
> On Sat, Apr 25, 2026 at 09:33:07PM +0900, Akinobu Mita wrote:
> > 2026年4月25日(土) 8:31 SeongJae Park <sj@kernel.org>:
[...]
> > import perf
> > 
> > if __name__ == '__main__':
> >     evlist = perf.parse_events("mem-loads")
> >     for evsel in evlist:
> >         print(f"{evsel}: type={evsel.type} config={evsel.config}")
> 
> It'd be great if we could have something like this.  Currently we have
> libperf (in C) in tools/lib/perf but it doesn't have the parser yet.
> 
> Anyway there are vendor-contributed event/metric description in JSON
> under tools/perf/pmu-events/arch directory.  You may extract the event
> encoding from the JSON and convert it using the sysfs format info.
> 
> On Alderlake, the 'mem_trans_retired.load_latency_gt_1024' is defined
> like below:
> 
> tools/perf/pmu-events/arch/x86/alderlake/memory.json +128
> 
>     {
>         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
>         "Counter": "1,2,3,4,5,6,7",
>         "Data_LA": "1",
>         "EventCode": "0xcd",
>         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
>         "MSRIndex": "0x3F6",
>         "MSRValue": "0x400",
>         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.  Reported latency may be longer than just the memory latency.",
>         "SampleAfterValue": "53",
>         "UMask": "0x1",
>         "Unit": "cpu_core"
>     },
> 
> I think MSRValue is for attr.config1.

Oh great.  Thank you for kindly sharing this Namhyung!  This makes me feel perf
event based DAMON monitoring even more promising!


Thanks,
SJ

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