From: sashiko-bot@kernel.org
To: "Dapeng Mi" <dapeng1.mi@linux.intel.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 07/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for ARL
Date: Fri, 15 May 2026 06:40:20 +0000 [thread overview]
Message-ID: <20260515064020.AF597C2BCC7@smtp.kernel.org> (raw)
In-Reply-To: <20260515061143.338553-8-dapeng1.mi@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Unhandled memory allocation failure in intel_pmu_init_hybrid() leads to a NULL pointer dereference.
--
commit e86d9a7a48c7a21c02757243f3a40ac6b6e47297
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
perf/x86/intel: Update event constraints and cache_extra_regs[] for ARL
Updates perf hard-coded event constraints and cache_extra_regs[] for
Arrowlake. Introduces ARL-specific arl_lnc_hw_cache_extra_regs and adds
crestmont specific constraints for LPE cores.
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
[ ... ]
> @@ -8529,16 +8547,41 @@ __init int intel_pmu_init(void)
> case INTEL_WILDCATLAKE_L:
> pr_cont("Pantherlake Hybrid events, ");
> name = "pantherlake_hybrid";
> +
> + intel_pmu_init_hybrid(hybrid_big_small);
> +
> + /* Initialize big core specific PerfMon capabilities.*/
> + pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
> + intel_pmu_init_lnc(&pmu->pmu);
> +
> goto lnl_common;
>
> - case INTEL_LUNARLAKE_M:
> case INTEL_ARROWLAKE:
> + pr_cont("Arrowlake Hybrid events, ");
> + name = "arrowlake_hybrid";
> +
> + intel_pmu_init_hybrid(hybrid_big_small);
> +
> + /* Initialize big core specific PerfMon capabilities.*/
> + pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
> + intel_pmu_init_lnc(&pmu->pmu);
Does this code risk a NULL pointer dereference if the memory allocation in
intel_pmu_init_hybrid() fails?
Looking at intel_pmu_init_hybrid(), it allocates x86_pmu.hybrid_pmu and
returns -ENOMEM if kzalloc_objs() fails.
If that allocation fails here, the return value is ignored. The code
immediately proceeds to calculate the pmu pointer using x86_pmu.hybrid_pmu
and passes it to intel_pmu_init_lnc(), which would dereference it.
While this pattern existed before this patch, it is being propagated into
the new Pantherlake and Arrowlake initialization blocks. Could we add error
handling here to catch the allocation failure before accessing the array?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515061143.338553-1-dapeng1.mi@linux.intel.com?part=7
next prev parent reply other threads:[~2026-05-15 6:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 6:11 [PATCH 00/11] perf/x86/intel: Fix inaccurate hard-coded event configurations Dapeng Mi
2026-05-15 6:11 ` [PATCH 01/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for ICX Dapeng Mi
2026-05-15 6:11 ` [PATCH 02/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for SPR Dapeng Mi
2026-05-15 6:11 ` [PATCH 03/11] perf/x86/intel: Update event constraints for DMR Dapeng Mi
2026-05-15 6:11 ` [PATCH 04/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for ADL Dapeng Mi
2026-05-15 6:38 ` sashiko-bot
2026-05-15 6:11 ` [PATCH 05/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for MTL Dapeng Mi
2026-05-15 6:11 ` [PATCH 06/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for LNL Dapeng Mi
2026-05-15 6:11 ` [PATCH 07/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for ARL Dapeng Mi
2026-05-15 6:40 ` sashiko-bot [this message]
2026-05-15 6:11 ` [PATCH 08/11] perf/x86/intel: Update event constraints for PTL Dapeng Mi
2026-05-15 6:11 ` [PATCH 09/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for NVL Dapeng Mi
2026-05-15 6:11 ` [PATCH 10/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for SRF Dapeng Mi
2026-05-15 6:11 ` [PATCH 11/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for CWF Dapeng Mi
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