[PATCH v2 0/2] Add IOMMU TLB and interrupt metrics

[Chun-Tse Shao <ctshao@google.com>]

This patch series adds IOMMU Translation Lookaside Buffer (TLB) and
interrupt cache metrics to perf jevents for both AMD and Intel platforms.
This enhances I/O performance observability, allowing fleet-wide monitoring
of IOMMU overhead.

The changes are split into two patches:
1. perf jevents: Add IOMMU metrics for AMD
   - Adds IOMMU TLB and interrupt metrics for Zen 2+ processors using
     standard AMD IOMMU PMU events.
   - Note that pde events on AMD cover both 2M and 1G pages, so 1G pages
     are implicitly included.
   - Added code comments to clarify this hardware detail and fixed
     indentation to match the file's style.

2. perf jevents: Add IOMMU metrics for Intel
   - Adds IOMMU TLB and interrupt metrics using uncore IIO IOMMU events.
   - Supports Emerald Rapids (TLB-only) and Granite Rapids (TLB +
     Interrupt) by dynamically detecting event availability and making
     interrupt metrics optional.
   - Clamped calculated interrupt cache miss metric to zero to prevent
     negative values due to counter multiplexing or sampling skid.

v2:
  Split the changes into separate AMD and Intel commits as requested.

v1: lore.kernel.org/20260527223917.3845056-1-ctshao@google.com

Chun-Tse Shao (2):
  perf jevents: Add IOMMU metrics for AMD
  perf jevents: Add IOMMU metrics for Intel

 tools/perf/pmu-events/amd_metrics.py   | 57 +++++++++++++++++++++++
 tools/perf/pmu-events/intel_metrics.py | 62 ++++++++++++++++++++++++++
 2 files changed, 119 insertions(+)

--
2.54.0.823.g6e5bcc1fc9-goog