From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Sandipan Das <sandipan.das@amd.com>
Cc: Chun-Tse Shao <ctshao@google.com>,
Perry Taylor <perry.taylor@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] perf jevents: Add IOMMU metrics for AMD
Date: Fri, 29 May 2026 21:11:20 -0300 [thread overview]
Message-ID: <ahorKGXDiajCrTMA@x1> (raw)
In-Reply-To: <300855bd-c4fd-4915-8a93-8671377493b3@amd.com>
On Fri, May 29, 2026 at 02:56:38PM +0530, Sandipan Das wrote:
> On 29-05-2026 05:14, Chun-Tse Shao wrote:
> > Add IOMMU Translation Lookaside Buffer (TLB) and interrupt cache metrics
> > to perf jevents for AMD platforms. This enhances I/O performance
> > observability, allowing fleet-wide monitoring of IOMMU overhead.
> >
> > These metrics are supported on Zen 2 and newer processors (Rome, Milan,
> > Genoa, Turin) and are implemented using the standard `amd_iommu` PMU
> > events. The implementation uses the existing `_zen_model` helper to
> > ensure these are only generated for Zen 2+. Note that the pde events on
> > AMD cover both 2M and 1G pages, so 1G pages are implicitly included in
> > the total hits/misses metrics (sum of pte and pde events).
> >
> > The following metrics are added:
> > - iotlb_total_hit: Total IOTLB hits (4K, 2M, 1G pages).
> > - iotlb_total_miss: Total IOTLB misses.
> > - iotlb_miss_rate: IOTLB miss rate.
> > - iotlb_interrupt_cache_hit: Interrupt cache hits.
> > - iotlb_interrupt_cache_miss: Interrupt cache misses.
> > - iotlb_interrupt_cache_lookup: Interrupt cache lookups.
> > - iotlb_interrupt_cache_miss_rate: Interrupt cache miss rate.
> >
> > Tested:
> > # perf stat -M \
> > iotlb_total_hit,iotlb_total_miss,iotlb_miss_rate \
> > --per-socket --metric-only -a -j -- sleep 10
> > {"socket" : "S0", "counters" : 10,
> > "hits iotlb_total_hit" : "3579249.0",
> > "% iotlb_miss_rate" : "0.0",
> > "misses iotlb_total_miss" : "3.0"}
> > {"socket" : "S1", "counters" : 10,
> > "hits iotlb_total_hit" : "0.0",
> > "% iotlb_miss_rate" : "0.0",
> > "misses iotlb_total_miss" : "0.0"}
> >
> > Signed-off-by: Chun-Tse Shao <ctshao@google.com>
> > Assisted-by: Gemini:gemini-3.1-pro-preview
> > ---
>
> Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Thanks, applied both patches and collected Ian's reviewed-by, since he
provided it for the combined patch and requested that it was split,
which this v2 does.
- Arnaldo
next prev parent reply other threads:[~2026-05-30 0:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 23:44 [PATCH v2 0/2] Add IOMMU TLB and interrupt metrics Chun-Tse Shao
2026-05-28 23:44 ` [PATCH v2 1/2] perf jevents: Add IOMMU metrics for AMD Chun-Tse Shao
2026-05-29 9:26 ` Sandipan Das
2026-05-30 0:11 ` Arnaldo Carvalho de Melo [this message]
2026-05-28 23:44 ` [PATCH v2 2/2] perf jevents: Add IOMMU metrics for Intel Chun-Tse Shao
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