Re: [PATCH v7] perf test: Remove /usr/bin/cc dependency from Intel PT shell test

Re: [PATCH v7] perf test: Remove /usr/bin/cc dependency from Intel PT shell test

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Instruction encodings on AArch64 and RISC-V incorrectly assume the host data byte order dictates instruction fetch byte order.
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commit 24bba6efa576b6453f0f09427882a8cfb7205892
Author: Ian Rogers <irogers@google.com>

perf test: Remove /usr/bin/cc dependency from Intel PT shell test

This commit replaces the external C compiler dependency in the Intel PT shell
test with a built-in jitdump workload. It dynamically encodes instructions
across multiple architectures to avoid requiring an external compiler at
runtime.

[ ... ]

> diff --git a/tools/perf/tests/workloads/jitdump.c b/tools/perf/tests/workloads/jitdump.c
> new file mode 100644
> index 0000000000000..6bbe703c84092
> --- /dev/null
> +++ b/tools/perf/tests/workloads/jitdump.c

[ ... ]

> +static int jitdump(int argc __maybe_unused, const char **argv __maybe_unused)
> +{
> +#if defined(__x86_64__) || defined(__i386__)
> +	/* Code to execute: mov CHK_BYTE, %eax ; ret */
> +	uint8_t dat[] = { 0xb8, CHK_BYTE, 0x00, 0x00, 0x00, 0xc3 };
> +#elif defined(__aarch64__)
> +	/* Code to execute: mov w0, #CHK_BYTE ; ret */
> +	uint32_t dat[] = { 0x52800000 | (CHK_BYTE << 5), 0xd65f03c0 };
> +#elif defined(__riscv)
> +	/* Code to execute: li a0, CHK_BYTE ; ret */
> +	uint32_t dat[] = { ((CHK_BYTE & 0xfff) << 20) | 0x513, 0x00008067 };

[Severity: Medium]
Will this execute invalid instructions on big-endian AArch64 and RISC-V systems?

The specifications for these architectures mandate that instructions are
always fetched in little-endian byte order, regardless of the data endianness
configuration of the cpu. By defining the dynamic instructions as a uint32_t
array, the code relies on the host compiler's data layout.

When compiled on a big-endian host, the compiler stores these uint32_t values
in big-endian byte order in memory. When the cpu subsequently fetches this
memory to execute, it reads the bytes as a little-endian instruction word,
effectively byte-swapping the instruction. This results in the execution of
invalid or unintended instructions and causes the perf test to fail.

Would it be safer to encode these architectures using byte arrays in
little-endian order to ensure correctness on big-endian hosts?

> +#elif defined(__powerpc__)
> +	/* Code to execute: li r3, CHK_BYTE ; blr */
> +	uint32_t dat[] = { 0x38600000 | (CHK_BYTE & 0xffff), 0x4e800020 };

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260602073132.2653307-17-irogers@google.com?part=1