[PATCH RFC] dt-bindings: perf: riscv,pmu: Add interrupts-extended property

[PATCH RFC] dt-bindings: perf: riscv,pmu: Add interrupts-extended property

[Eric Lin]

The interrupts-extended property is used to specify the connection
between the PMU counter overflow interrupt and the corresponding CPU
local interrupt controller (riscv,cpu-intc).

This property also allows the software to associate a PMU node with a
specific CPU. To support future heterogeneous systems, where different
CPUs may support different PMU events, this property allows the driver
to identify the correct PMU capabilities for each hart.

Reviewed-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Eric Lin <eric.lin@sifive.com>
---
 Documentation/devicetree/bindings/perf/riscv,pmu.yaml | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
index d01c677ad3c7..13aceb3d42b9 100644
--- a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
+++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
@@ -34,6 +34,13 @@ properties:
   compatible:
     const: riscv,pmu
 
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+    description:
+      Specifies the interrupt-parent and local interrupt index for each CPU's
+      PMU counter overflow. Each item points to a riscv,cpu-intc node.
+
   riscv,event-to-mhpmevent:
     $ref: /schemas/types.yaml#/definitions/uint32-matrix
     description:
@@ -101,6 +108,7 @@ examples:
   - |
     pmu {
         compatible = "riscv,pmu";
+        interrupts-extended = <&cpu0_intc 13>;
         riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
         riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
                                       <0x00002 0x00002 0x00000004>,
@@ -127,6 +135,9 @@ examples:
      */
     pmu {
           compatible = "riscv,pmu";
+          interrupts-extended = <&cpu0_intc 13>,
+                                <&cpu1_intc 13>,<&cpu2_intc 13>,
+                                <&cpu3_intc 13>,<&cpu4_intc 13>;
           riscv,event-to-mhpmevent =
               /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
               <0x00003 0x00000000 0x1801>,

---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260701-pmu-dt-property-ff12b35fe0fc

Best regards,
--  
Eric Lin <eric.lin@sifive.com>

Re: [PATCH RFC] dt-bindings: perf: riscv,pmu: Add interrupts-extended property

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Overloading `interrupts-extended` as the sole CPU affinity map fails when PMU interrupts are optional.
--

commit c04ae2b471021dd39ca8ccf1e788362245660a9d
Author: Eric Lin <eric.lin@sifive.com>

dt-bindings: perf: riscv,pmu: Add interrupts-extended property

This commit adds the interrupts-extended property to the riscv,pmu binding
to define the connection between the PMU overflow interrupt and the CPU
local interrupt controller. It also notes this property is used by software
to associate a PMU node with a specific CPU on heterogeneous systems.

> diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> --- a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> @@ -34,6 +34,13 @@ properties:
>    compatible:
>      const: riscv,pmu
>  
> +  interrupts-extended:
> +    minItems: 1
> +    maxItems: 4095
> +    description:
> +      Specifies the interrupt-parent and local interrupt index for each CPU's
> +      PMU counter overflow. Each item points to a riscv,cpu-intc node.

[Severity: Medium]
Does overloading interrupts-extended as the sole CPU affinity map cause
failures on systems without PMU interrupts?

If a heterogeneous RISC-V SoC lacks the optional Sscofpmf extension, it
would omit the interrupts-extended property entirely. Without this property,
it seems the OS would have no mechanism to determine which PMU node belongs
to which CPU, potentially breaking perf functionality on such hardware.

Would it be safer to introduce a dedicated affinity property to prevent
future fragmentation when PMU interrupts are absent?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702-pmu-dt-property-v1-1-a7a7737afb72@sifive.com?part=1