* [PATCH] perf jevents: Add Intel OMR MSR mappings
@ 2026-07-08 5:32 Dapeng Mi
0 siblings, 0 replies; only message in thread
From: Dapeng Mi @ 2026-07-08 5:32 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin
Cc: linux-perf-users, linux-kernel, Zide Chen, Falcon Thomas,
Dapeng Mi, Xudong Hao, Dapeng Mi
New OMR MSRs are introduced for OMR events on DMR and NVL. Perf continues
to reuse the existing offcore_rsp attribute to encode the MSR value,
similar to existing OCR event handling.
Add the corresponding OMR MSR mappings in lookup_msr() so jevents can
translate these events and generate the correct offcore_rsp attribute.
Link: https://lore.kernel.org/all/20260114011750.350569-2-dapeng1.mi@linux.intel.com/
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
tools/perf/pmu-events/jevents.py | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index 376dc2d24162..2bb51cc621b5 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -249,6 +249,10 @@ class JsonEvent:
0x3F6: 'ldlat=',
0x1A6: 'offcore_rsp=',
0x1A7: 'offcore_rsp=',
+ 0x3E0: 'offcore_rsp=',
+ 0x3E1: 'offcore_rsp=',
+ 0x3E2: 'offcore_rsp=',
+ 0x3E3: 'offcore_rsp=',
0x3F7: 'frontend=',
}
return msrmap[int(num.split(',', 1)[0], 0)]
--
2.34.1
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