From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH 7/7] perf/x86: Optimize ACR handling in match_prev_assignment()
Date: Fri, 10 Jul 2026 14:51:28 +0800 [thread overview]
Message-ID: <20260710065128.1799838-8-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20260710065128.1799838-1-dapeng1.mi@linux.intel.com>
match_prev_assignment() currently forces a mismatch for ACR events, so
ACR counter indices are reprogrammed on every scheduling pass. That
causes avoidable overhead because disable and enable paths must touch
multiple MSRs.
The previous ACR assignment is already cached in acr_cfg_b[]. Use that
state to compare the newly computed ACR counter indices in hwc->config1
against the cached value in acr_cfg_b[hwc->idx]. If they match, skip
unnecessary disable and enable work.
Also tighten is_acr_self_reload_event() so it first verifies the event
is an ACR event before testing for the self-reload case.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/core.c | 13 ++++++++++++-
arch/x86/events/perf_event.h | 2 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 0bd3798b6e33..6a7502d2ae6e 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1292,6 +1292,17 @@ int x86_perf_rdpmc_index(struct perf_event *event)
return event->hw.event_base_rdpmc;
}
+static inline bool acr_match_prev_indices(struct perf_event *event,
+ struct cpu_hw_events *cpuc)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ if (!is_acr_event_group(event))
+ return true;
+ /* ACR counter indices don't change. */
+ return hwc->config1 == cpuc->acr_cfg_b[hwc->idx];
+}
+
static inline int match_prev_assignment(struct perf_event *event,
struct cpu_hw_events *cpuc,
int i)
@@ -1301,7 +1312,7 @@ static inline int match_prev_assignment(struct perf_event *event,
return hwc->idx == cpuc->assign[i] &&
hwc->last_cpu == smp_processor_id() &&
hwc->last_tag == cpuc->tags[i] &&
- !is_acr_event_group(event);
+ acr_match_prev_indices(event, cpuc);
}
static void x86_pmu_start(struct perf_event *event, int flags);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 088f7ce715df..d382e5ed72a8 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -141,7 +141,7 @@ static inline bool is_acr_self_reload_event(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
- if (hwc->idx < 0)
+ if (hwc->idx < 0 || !is_acr_event_group(event))
return false;
return test_bit(hwc->idx, (unsigned long *)&hwc->config1);
--
2.34.1
prev parent reply other threads:[~2026-07-10 6:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 6:51 [PATCH 0/7] perf/x86: Miscellaneous PMU bug fixes and optimizations Dapeng Mi
2026-07-10 6:51 ` [PATCH 1/7] perf/x86: Unregister PMI handler on PMU init failure Dapeng Mi
2026-07-10 6:51 ` [PATCH 2/7] perf/x86: Free hybrid state " Dapeng Mi
2026-07-10 6:51 ` [PATCH 3/7] perf/x86/intel: Clear cpuc->pmu on hybrid " Dapeng Mi
2026-07-10 7:26 ` sashiko-bot
2026-07-10 8:01 ` Mi, Dapeng
2026-07-10 8:20 ` Mi, Dapeng
2026-07-10 6:51 ` [PATCH 4/7] perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails Dapeng Mi
2026-07-10 6:51 ` [PATCH 5/7] perf/x86: Remove stale fixed counter helper and fix hybrid PMU access Dapeng Mi
2026-07-10 6:51 ` [PATCH 6/7] perf/x86/intel: Fix intel_cap handling on hybrid PMUs Dapeng Mi
2026-07-10 6:51 ` Dapeng Mi [this message]
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