From: Jonathan Cameron <jic23@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Dave Jiang <dave.jiang@intel.com>,
linux-cxl@vger.kernel.org, linux-perf-users@vger.kernel.org,
will@kernel.org, mark.rutland@arm.com, dave@stgolabs.net,
sashiko-bot@kernel.org
Subject: Re: [PATCH v2 6/9] perf/cxl: Unfreeze counters after handling an overflow interrupt
Date: Thu, 30 Jul 2026 19:53:13 +0100 [thread overview]
Message-ID: <20260730195313.3e2c0b8e@jic23-huawei> (raw)
In-Reply-To: <3dc5c366-652f-4977-84a1-6e5a921a74cc@arm.com>
On Thu, 30 Jul 2026 13:04:17 +0100
Robin Murphy <robin.murphy@arm.com> wrote:
> On 29/07/2026 3:55 pm, Dave Jiang wrote:
> > The counters are configured with Freeze on Overflow, so when any counter
> > overflows the CPMU freezes every counter in the block (CXL r4.0
> > §8.2.7.2.1). cxl_pmu_irq() reads the overflowed counters and clears the
> > overflow status, but never writes the CPMU Freeze register to unfreeze,
> > so all counters stay frozen until the next pmu_enable() and events in
> > that window are silently lost.
> >
> > Unfreeze after clearing the overflow status so counting resumes.
> >
> > Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
> > Reported-by: sashiko-bot@kernel.org
> > Closes: https://sashiko.dev/#/patchset/20260715191454.459673-1-dave@stgolabs.net?part=1
> > Assisted-by: Claude:claude-opus-4-8
> > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > ---
> > drivers/perf/cxl_pmu.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> > index 8b89db8f4d68..52e78a6e0960 100644
> > --- a/drivers/perf/cxl_pmu.c
> > +++ b/drivers/perf/cxl_pmu.c
> > @@ -804,6 +804,15 @@ static irqreturn_t cxl_pmu_irq(int irq, void *data)
> >
> > writeq(overflowed, base + CXL_PMU_OVERFLOW_REG);
> >
> > + /*
> > + * Counters are configured to freeze on overflow (Freeze on Overflow),
> > + * which freezes every counter in the CPMU. Once the overflowed counters
> > + * have been read and their status cleared, unfreeze so counting resumes;
> > + * otherwise all counters stay frozen until the next pmu_enable() and
> > + * events are silently lost.
> > + */
> > + writeq(0, base + CXL_PMU_FREEZE_REG);
>
> Does this unconditionally unfreeze _all_ counters, including any which
> might have have overflowed since the read of CXL_PMU_OVERFLOW_REG and
> thus have not been handled yet? Or are we hoping that the "global
> freeze" behaviour prevents that from being able to happen?
>
Yes global freeze should stop world on first one overflowing - if two go together
we should see them both in the handler.
> Furthermore, what if an overflow happens to occur just as
> cxl_pmu_disable() is intentionally freezing all the counters, such that
> by the time we get here, unfreezing them would be the wrong thing to do?
Hmm. That may indeed be bad.
>
> Thanks,
> Robin.
>
> > +
> > return IRQ_HANDLED;
> > }
> >
>
next prev parent reply other threads:[~2026-07-30 18:53 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 14:55 [PATCH v2 0/9] perf/cxlpmu: Misc sashiko raised issues fixes Dave Jiang
2026-07-29 14:55 ` [PATCH v2 1/9] perf/cxl: Program the requested event group on configurable counters Dave Jiang
2026-07-29 15:06 ` sashiko-bot
2026-07-29 22:29 ` Jonathan Cameron
2026-07-30 15:50 ` Dave Jiang
2026-07-29 14:55 ` [PATCH v2 2/9] perf/cxl: Clear stale event fields before reprogramming a counter Dave Jiang
2026-07-29 15:08 ` sashiko-bot
2026-07-29 22:25 ` Jonathan Cameron
2026-07-30 15:45 ` Dave Jiang
2026-07-29 14:55 ` [PATCH v2 3/9] perf/cxl: Fix the counter overflow delta fixup Dave Jiang
2026-07-29 15:13 ` sashiko-bot
2026-07-29 22:21 ` Jonathan Cameron
2026-07-30 16:56 ` Dave Jiang
2026-07-30 17:19 ` Dave Jiang
2026-07-30 19:00 ` Jonathan Cameron
2026-07-29 14:55 ` [PATCH v2 4/9] perf/cxl: Accept an overflow interrupt on MSI message number 0 Dave Jiang
2026-07-29 19:28 ` Jonathan Cameron
2026-07-29 19:59 ` Davidlohr Bueso
2026-07-30 12:18 ` Robin Murphy
2026-07-30 17:57 ` Dave Jiang
2026-07-30 18:57 ` Jonathan Cameron
2026-07-30 21:32 ` Dave Jiang
2026-07-29 14:55 ` [PATCH v2 5/9] perf/cxl: Keep the overflow interrupt pinned to the managed CPU Dave Jiang
2026-07-29 15:23 ` sashiko-bot
2026-07-29 19:25 ` Jonathan Cameron
2026-07-29 20:27 ` Davidlohr Bueso
2026-07-30 11:46 ` Robin Murphy
2026-07-30 18:55 ` Jonathan Cameron
2026-07-30 21:34 ` Dave Jiang
2026-07-30 22:19 ` Dave Jiang
2026-07-29 14:55 ` [PATCH v2 6/9] perf/cxl: Unfreeze counters after handling an overflow interrupt Dave Jiang
2026-07-29 19:24 ` Jonathan Cameron
2026-07-30 12:04 ` Robin Murphy
2026-07-30 18:53 ` Jonathan Cameron [this message]
2026-07-30 23:00 ` Dave Jiang
2026-07-29 14:55 ` [PATCH v2 7/9] perf/cxl: Validate the hardware-reported counter width Dave Jiang
2026-07-29 15:11 ` sashiko-bot
2026-07-29 19:21 ` Jonathan Cameron
2026-07-29 14:55 ` [PATCH v2 8/9] perf/cxl: Don't use pmu.dev in IRQ and hotplug callbacks after unregister Dave Jiang
2026-07-29 15:34 ` sashiko-bot
2026-07-29 19:17 ` Jonathan Cameron
2026-07-30 11:38 ` Robin Murphy
2026-07-30 18:51 ` Jonathan Cameron
2026-07-29 14:55 ` [PATCH v2 9/9] perf/cxl: Avoid cpumask_of(-1) when no CPU is assigned Dave Jiang
2026-07-29 15:19 ` sashiko-bot
2026-07-29 19:14 ` Jonathan Cameron
2026-07-30 9:36 ` Robin Murphy
2026-07-31 0:11 ` Dave Jiang
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