From: Besar Wicaksono <bwicaksono@nvidia.com>
To: <john.g.garry@oracle.com>, <will@kernel.org>,
<james.clark@linaro.org>, <mike.leach@linaro.org>,
<leo.yan@linux.dev>, <mark.rutland@arm.com>,
<alexander.shishkin@linux.intel.com>, <jolsa@kernel.org>,
<irogers@google.com>, <adrian.hunter@intel.com>,
<peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>,
<namhyung@kernel.org>
Cc: <linux-tegra@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <tmakin@nvidia.com>,
<vsethi@nvidia.com>, <rwiley@nvidia.com>, <skelley@nvidia.com>,
<rajjoshi@nvidia.com>, <treding@nvidia.com>,
<jonathanh@nvidia.com>, <mochs@nvidia.com>, <sauravsc@amazon.com>,
"Besar Wicaksono" <bwicaksono@nvidia.com>
Subject: [PATCH 2/2] perf vendor events arm64: Fix Tegra410 Olympus event 0x0197
Date: Thu, 13 Aug 2026 17:01:55 +0000 [thread overview]
Message-ID: <20260813170155.1156593-3-bwicaksono@nvidia.com> (raw)
In-Reply-To: <20260813170155.1156593-1-bwicaksono@nvidia.com>
The name and description for NVIDIA Tegra410 Olympus implementation-defined
event 0x0197 incorrectly indicate a TXREQ limit between one quarter and
one half. Correct them to describe a TXREQ limit below one half.
Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events")
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json
index 8ff87d844e52..e1b45cc33b18 100644
--- a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json
@@ -316,8 +316,8 @@
},
{
"EventCode": "0x0197",
- "EventName": "TXREQ_LIMIT_1QUARTER_CYCLES",
- "PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 1/4 of the L2_TQ_SIZE and 1/2 of the L2_TQ_SIZE."
+ "EventName": "TXREQ_LIMIT_BELOW_HALF_CYCLES",
+ "PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 0 and 1/2 of the L2_TQ_SIZE."
},
{
"EventCode": "0x019d",
@@ -517,7 +517,7 @@
{
"EventCode": "0x01cc",
"EventName": "TXREQ_LIMIT_COUNT_CYCLES",
- "PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_1QUARTER_CYCLES."
+ "PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_BELOW_HALF_CYCLES."
},
{
"EventCode": "0x01ce",
--
2.43.0
next prev parent reply other threads:[~2026-08-13 17:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-13 17:01 [PATCH 0/2] perf vendor events arm64: Fix Tegra410 Olympus PMU events Besar Wicaksono
2026-08-13 17:01 ` [PATCH 1/2] perf vendor events arm64: fix swapped MetricGroup for Tegra410 L1 prefetcher metrics Besar Wicaksono
2026-08-13 17:11 ` sashiko-bot
2026-08-13 17:01 ` Besar Wicaksono [this message]
2026-08-13 17:08 ` [PATCH 2/2] perf vendor events arm64: Fix Tegra410 Olympus event 0x0197 sashiko-bot
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