From: sashiko-bot@kernel.org
To: "Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v10 4/9] drivers: firmware: add riscv SSE support
Date: Fri, 11 Sep 2026 12:35:34 +0000 [thread overview]
Message-ID: <20260911123534.6D1C11F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260911121456.33223-5-zhangzhanpeng.jasper@bytedance.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] lockdep_assert_preemption_disabled() in local event functions triggers a lockdep splat when called from CPU hotplug callbacks.
--
commit c8e18c554b3059a878f2a5763162d36f8061a2de
Author: Clément Léger <cleger@rivosinc.com>
drivers: firmware: add riscv SSE support
This commit adds a driver-level interface for RISC-V Supervisor Software
Events (SSE). It allows Linux clients to register NMI-like event handlers,
select target CPUs, and manage global or local events while handling CPU
hotplug and firmware interactions.
> diff --git a/drivers/firmware/riscv/riscv_sbi_sse.c b/drivers/firmware/riscv/riscv_sbi_sse.c
> new file mode 100644
> index 0000000000000..e81cfb4b0c563
> --- /dev/null
> +++ b/drivers/firmware/riscv/riscv_sbi_sse.c
[ ... ]
> +int sse_event_disable_local(struct sse_event *event)
> +{
> + if (!sse_event_is_global(event->evt_id))
> + lockdep_assert_preemption_disabled();
> +
> + if (!sse_get_reg_evt(event)->is_enabled)
> + return 0;
> +
> + return sse_sbi_event_func(event, SBI_SSE_EVENT_DISABLE);
> +}
> +EXPORT_SYMBOL_GPL(sse_event_disable_local);
> +
> +int sse_event_enable_local(struct sse_event *event)
> +{
> + struct sse_registered_event *reg_evt = sse_get_reg_evt(event);
> + int ret;
> +
> + if (!sse_event_is_global(event->evt_id))
> + lockdep_assert_preemption_disabled();
[ ... ]
> +static int sse_cpu_online(unsigned int cpu)
> +{
> + int ret, rollback_ret;
> + struct sse_event *event, *tmp;
> + struct sse_registered_event *reg_evt;
> +
> + arch_sse_init_cpu();
> +
> + list_for_each_entry_safe(event, tmp, &events, list) {
> + if (sse_event_is_global(event->evt_id))
> + continue;
> + if (event->cleanup_pending) {
> + ret = sse_teardown_event(event, cpu);
> + if (ret)
> + goto rollback;
> + sse_release_cleanup_event(event);
> + continue;
> + }
> +
> + ret = sse_event_register_local(event);
> + if (ret)
> + goto rollback;
> + if (event->enable_requested)
> + ret = sse_event_enable_local(event);
> + else
> + ret = sse_event_disable_local(event);
[Severity: Medium]
Will this lockdep assertion trigger a warning during CPU hotplug operations?
The CPU hotplug callback sse_cpu_online() (as well as sse_cpu_teardown() via
sse_teardown_event()) runs from the hotplug thread with preemption enabled.
When these callbacks process local events, they directly invoke
sse_event_enable_local() and sse_event_disable_local(). Because those
functions enforce lockdep_assert_preemption_disabled() for local events,
could this cause a lockdep splat whenever a CPU is brought online or offline?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260911121456.33223-1-zhangzhanpeng.jasper@bytedance.com?part=4
next prev parent reply other threads:[~2026-09-11 12:35 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 12:14 [PATCH v10 0/9] riscv: add SBI Supervisor Software Events support Zhanpeng Zhang
2026-09-11 12:14 ` [PATCH v10 1/9] riscv: add SBI SSE extension definitions Zhanpeng Zhang
2026-09-11 12:20 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 2/9] riscv: add support for SBI Supervisor Software Events extension Zhanpeng Zhang
2026-09-11 12:34 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 3/9] riscv: sse: mask events during shutdown and kexec Zhanpeng Zhang
2026-09-11 12:30 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 4/9] drivers: firmware: add riscv SSE support Zhanpeng Zhang
2026-09-11 12:35 ` sashiko-bot [this message]
2026-09-11 12:14 ` [PATCH v10 5/9] riscv: mm: avoid enabling interrupts for nofault page faults Zhanpeng Zhang
2026-09-11 12:28 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 6/9] perf: RISC-V: support callchains with SSE delivery Zhanpeng Zhang
2026-09-11 12:35 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 7/9] perf: RISC-V: add support for SSE event Zhanpeng Zhang
2026-09-11 12:37 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 8/9] selftests/riscv: add SSE test module Zhanpeng Zhang
2026-09-11 12:40 ` sashiko-bot
2026-09-11 12:14 ` [PATCH v10 9/9] selftests/riscv: add perf user-stack SSE copy regression test Zhanpeng Zhang
2026-09-11 12:33 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260911123534.6D1C11F00893@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=zhangzhanpeng.jasper@bytedance.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox